JAJSCQ3E October   2016  – January 2021 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8.     15
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
サーマルパッド・メカニカル・データ
発注情報

7.3.6 PWM Motor Gate Drivers

The DRV870x-Q1 device has gate drivers for a single H-bridge with external NMOS FETs. Figure 7-9 shows a block diagram of the predrive circuitry.

GUID-75D57921-B9E6-4910-AC0C-D9D05F2745C4-low.gif Figure 7-9 Predrive Block Diagram

Gate drivers inside the DRV870x-Q1 device directly drive N-Channel MOSFETs, which drive the motor current. The high-side gate drive is supplied by the charge pump, while an internal regulator generates the low-side gate drive.

The peak drive current of the gate drivers is adjustable through the IDRIVE pin for DRV8702-Q1 device or the IDRIVE register for the DRV8703-Q1 device. Peak source currents can be set to the values listed in the FET gate drivers section of the Section 6.5 table. The peak sink current is approximately two times the peak source current. Adjusting the peak current changes the output slew rate, which also depends on the FET input capacitance and gate charge.

Fast switching times can cause extra noise on the VM and GND pins. This additional noise can occur specifically because of a relatively slow reverse-recovery time of the low-side body diode, when the body diode conducts reverse-bias momentarily, similar to shoot-through. Slow switching times can cause excessive power dissipation because the external FETs have a longer turn on and turn off time.

When changing the state of the output, the peak current (IDRIVE) is applied for a short period (t(DRIVE)), to charge the gate capacitance. After this time, a weak current source (IHOLD) is used to keep the gate at the desired state. When selecting the gate drive strength for a given external FET, the selected current must be high enough to charge fully and discharge the gate during t(DRIVE), or excessive power is dissipated in the FET.

During high-side turn on, the low-side gate is pulled low with a strong pulldown (ISTRONG). This pulldown prevents the low-side FET QGS from charging and keeps the FET off, even when fast switching occurs at the outputs.

The gate-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and low-side FETs from conducting at the same time. When the switching FETs are on, this handshaking prevents the high-side or low-side FET from turning on until the opposite FET turns off.

GUID-3B68CDF1-25CB-4043-B575-D1300C724818-low.gifFigure 7-10 Gate Driver Output to Control External FETs