JAJSD22B March   2017  – December 2018 DRV8702D-Q1 , DRV8703D-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702D-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702D-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703D-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 DRV8703D-Q1 Memory Map
      2. 7.6.2 Status Registers
        1. 7.6.2.1 FAULT Status Register (address = 0x00h)
          1. Table 15. FAULT Status Field Descriptions
        2. 7.6.2.2 VDS and GDF Status Register Name (address = 0x01h)
          1. Table 16. VDS and GDF Status Field Descriptions
      3. 7.6.3 Control Registers
        1. 7.6.3.1 Main Control Register Name (address = 0x02h)
          1. Table 18. Main Control Field Descriptions
        2. 7.6.3.2 IDRIVE and WD Control Register Name (address = 0x03h)
          1. Table 19. IDRIVE and WD Field Descriptions
        3. 7.6.3.3 VDS Control Register Name (address = 0x04h)
          1. Table 21. VDS Control Field Descriptions
        4. 7.6.3.4 Config Control Register Name (address = 0x05h)
          1. Table 22. Config Control Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

Over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
t(SLEEP) Sleep time nSLEEP = low to sleep mode 100 µs
t(wu) Wake-up time nSLEEP = high to output change 1 ms
ton Turn on time VM > UVLO2 to output transition 1 ms
CHARGE PUMP (VCP, CPH, CPL)
fS(VCP) Charge-pump switching frequency VM > UVLO2 200 400 700 kHz
CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI, PH, EN)
tpd Propagation delay removed PH and EN pinsIN1, IN2 to GH or GL 500 ns
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
t(DEAD) Output dead time (DRV8702D-Q1) Observed t(DEAD) depends on IDRIVE setting 240 ns
t(DEAD) Output dead time (DRV8703D-Q1) TDEAD = 2’b00; Observed t(DEAD) depends on IDRIVE setting 120 ns
TDEAD = 2’b01; Observed t(DEAD) depends on IDRIVE setting 240
TDEAD = 2’b10; Observed t(DEAD) depends on IDRIVE setting 480
TDEAD = 2’b11; Observed t(DEAD) depends on IDRIVE setting 960
t(DRIVE) Gate drive time 2.5 µs
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
tS Settling time to ±1%(1) VSP = VSN = GND to VSP = 240 mV, VSN = GND, AV= 10; C(SO) = 200 pF 0.5 µs
VSP = VSN = GND to VSP = 120 mV, VSN = GND, AV= 20; C(SO) = 200 pF 1
VSP = VSN = GND to VSP = 60 mV, VSN = GND, AV= 40; C(SO) = 200 pF 2
VSP = VSN = GND to VSP = 30 mV, VSN = GND, AV= 80; C(SO) = 200 pF 4
toff PWM off-time (DRV8702D-Q1) 25 µs
toff PWM off-time (DRV8703D-Q1) TOFF = 00 25 µs
TOFF = 01 50
TOFF = 10 100
TOFF = 11 200
t(BLANK) PWM blanking time 2 µs
PROTECTION CIRCUITS
t(UVLO) VM UVLO falling deglitch time VM falling; UVLO report 10 µs
t(OCP) Overcurrent deglitch time 3.7 4 4.3 µs
t(RETRY) Overcurrent retry time 2.8 3 3.2 ms
t(WD) Watchdog time out (DRV8703D-Q1) WD_DLY = 2’b00 10 ms
WD_DLY = 2’b01 20
WD_DLY = 2’b10 50
WD_DLY = 2’b11 100
t(RESET) Watchdog timer reset period 64 µs
SPI
t(SPI_READY) SPI read after power on VM > VUVLO1 5 10 ms
td(SDO) SDO output data delay time, CLK high to SDO valid CL = 20 pF 30 ns
ta SCS access time, SCS low to SDO out of high impedance 10 ns
tdis SCS disable time, SCS high to SDO high impedance 10 ns
(1) Ensured by design
DRV8702D-Q1 DRV8703D-Q1 spi_slavemode_timingdefinition_slvs.gifFigure 1. SPI Slave Mode Timing Definition
DRV8702D-Q1 DRV8703D-Q1 spi_slavemode_timingdiagram_slvsdr9.gifFigure 2. SPI Slave Mode Timing Diagram