JAJSCQ3E October   2016  – January 2021 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8.     15
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
サーマルパッド・メカニカル・データ
発注情報

7.6 Register Maps

Table 7-14 DRV8703-Q1 Memory Map
Register
Name		76543210Access
Type		Address
(Hex)
FAULT StatusFAULTWDFLTGDFOCPVM_UVFLVCP_UVFLOTSDOTWR0
VDS and GDFH2_GDFL2_GDFH1_GDFL1_GDFH2_VDSL2_VDSH1_VDSL1_VDSR1
MainRESERVEDLOCKIN1/PHIN2/ENCLR_FLTRW2
IDRIVE and WDTDEADWD_ENWD_DLYIDRIVERW3
VDSSO_LIMVDSDIS_H2_VDSDIS_L2_VDSDIS_H1_VDSDIS_L1_VDSRW4
ConfigTOFFCHOP_IDSVREF_SCLSH_ENGAIN_CSRW5
Table 7-15 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite

7.6.1 Status Registers

The status registers are used to report warning and fault conditions. Status registers are read only registers.

Table 7-16 lists the memory-mapped registers for the status registers. All register offset addresses not listed in Table 7-16 should be considered as reserved locations and the register contents should not be modified.

Table 7-16 Status Registers Summary Table
AddressRegister NameSection
0x00hFAULT statusGo
0x01hVDS and GDF statusGo

7.6.2 FAULT Status Register (address = 0x00h)

FAULT status is shown in Figure 7-19 and described in Table 7-17.

Return to Summary Table.

Read only

Figure 7-19 FAULT Status Register
76543210
FAULTWDFLTGDFOCPVM_UVFLVCP_UVFLOTSDOTW
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-17 FAULT Status Field Descriptions
BitFieldTypeDefaultDescription
7FAULTR0b

Logic OR of the FAULT status register excluding the OTW bit

6WDFLTR0b

Watchdog time-out fault

5GDFR0b

Indicates gate drive fault condition

4OCPR0b

Indicates VDS monitor overcurrent fault condition

3VM_UVFLR0b

Indicates VM undervoltage lockout fault condition

2VCP_UVFLR0b

Indicates charge-pump undervoltage fault condition

1OTSDR0b

Indicates overtemperature shutdown

0OTWR0b

Indicates overtemperature warning

7.6.3 VDS and GDF Status Register Name (address = 0x01h)

VDS and GDF status is shown in Figure 7-20 and described in Table 7-18.

Return to Summary Table.

Read only

Figure 7-20 VDS and GDF Status Register
76543210
H2_GDFL2_GDFH1_GDFL1_GDFH2_VDSL2_VDSH1_VDSL1_VDS
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-18 VDS and GDF Status Field Descriptions
BitFieldTypeDefaultDescription
7H2_GDFR0b

Indicates gate drive fault on the high-side FET of half-bridge 2

6L2_GDFR0b

Indicates gate drive fault on the low-side FET of half-bridge 2

5H1_GDFR0b

Indicates gate drive fault on the high-side FET of half-bridge 1

4L1_GDFR0b

Indicates gate drive fault on the low-side FET of half-bridge 1

3H2_VDSR0b

Indicates VDS monitor overcurrent fault on the high-side FET of half-bridge 2

2L2_VDSR0b

Indicates VDS monitor overcurrent fault on the low-side FET of half-bridge 2

1H1_VDSR0b

Indicates VDS monitor overcurrent fault on the high-side FET of half-bridge 1

0L1_VDSR0b

Indicates VDS monitor overcurrent fault on the low-side FET of half-bridge 1

7.6.4 Control Registers

The control registers are used to configure the device. Control registers are read and write capable.

Table 7-19 lists the memory-mapped registers for the status registers. All register offset addresses not listed in Table 7-19 should be considered as reserved locations and the register contents should not be modified.

Table 7-19 Status Registers Summary Table
AddressRegister NameSection
0x02hMain controlGo
0x03hIDRIVE and WD controlGo
0x04hVDS controlGo
0x05hConfig controlGo

7.6.5 Main Control Register Name (address = 0x02h)

Main control is shown in Figure 7-21 and described in Table 7-20.

Return to Summary Table.

Read and write

Figure 7-21 Main Control Register
76543210
RESERVEDLOCKIN1/PHIN2/ENCLR_FLT
R/W-00bR/W-011bR/W-0bR/W-0bR/W-0b
Table 7-20 Main Control Field Descriptions
BitFieldTypeDefaultDescription
7-6RESERVEDR/W00b

Reserved

5-3LOCKR/W011b

Write 110b to lock the settings by ignoring further register changes except to address 0x02h. Writing any sequence other than 110b has no effect when unlocked.
Write 011b to this register to unlock all registers. Writing any sequence other than 011b has no effect when locked.

2IN1/PHR/W0b

This bit is ORed with the IN1/PH pin

1IN2/ENR/W0b

This bit is ORed with the IN2/EN pin

0CLR_FLTR/W0b

Write a 1 to this bit to clear the fault bits

7.6.6 IDRIVE and WD Control Register Name (address = 0x03h)

IDRIVE and WD control is shown in Figure 7-22 and described in Table 7-21.

Return to Summary Table.

Read and write

Figure 7-22 IDRIVE and WD Register
76543210
TDEADWD_ENWD_DLYIDRIVE
R/W-00bR/W-0bR/W-00bR/W-111b
Table 7-21 IDRIVE and WD Field Descriptions
BitFieldTypeDefaultDescription
7-6TDEADR/W00b

Dead time

00b = 120 ns

01b = 240 ns

10b = 480 ns

11b = 960 ns

5WD_ENR/W0b

Enables or disables the watchdog time (disabled by default)

4-3WD_DLYR/W00b

Watchdog timeout delay (if WD_EN = 1)

00b = 10 ms

01b = 20 ms

10b = 50 ms

11b = 100 ms

2-0IDRIVER/W111b

Sets the peak source current and peak sink current of the gate drive. Table 7-22 lists the bit settings.

Table 7-22 IDRIVE Bit Settings
Bit ValueSource CurrentSink Current
VVM = 5.5 VVVM = 13.5 VVVM = 5.5 VVVM = 13.5 V
000bHigh-side: 10 mA
Low-side: 10 mA		High-side: 10 mA
Low-side: 10 mA		High-side: 20 mA
Low-side: 20 mA		High-side: 20 mA
Low-side: 20 mA
001bHigh-side: 20 mA
Low-side: 20 mA		High-side: 20 mA
Low-side: 20 mA		High-side: 40 mA
Low-side: 40 mA		High-side: 40 mA
Low-side: 40 mA
010bHigh-side: 50 mA
Low-side: 40 mA		High-side: 50 mA
Low-side: 45 mA		High-side: 90 mA
Low-side: 85 mA		High-side: 95 mA
Low-side: 95 mA
011bHigh-side: 70 mA
Low-side: 55 mA		High-side: 70 mA
Low-side: 60 mA		High-side: 120 mA
Low-side: 115 mA		High-side: 130 mA
Low-side: 125 mA
100bHigh-side: 100 mA
Low-side: 75 mA		High-side: 105 mA
Low-side: 90 mA		High-side: 170 mA
Low-side: 160 mA		High-side: 185 mA
Low-side: 180 mA
101bHigh-side: 145 mA
Low-side: 115 mA		High-side: 155 mA
Low-side: 130 mA		High-side: 250 mA
Low-side: 235 mA		High-side: 265 mA
Low-side: 260 mA
110bHigh-side: 190 mA
Low-side: 145 mA		High-side: 210 mA
Low-side: 180 mA		High-side: 330 mA
Low-side: 300 mA		High-side: 350 mA
Low-side: 350 mA
111bHigh-side: 240 mA
Low-side: 190 mA		High-side: 260 mA
Low-side: 225 mA		High-side: 420 mA
Low-side: 360 mA		High-side: 440 mA
Low-side: 430 mA

7.6.7 VDS Control Register Name (address = 0x04h)

VDS control is shown in Figure 7-23 and described in Table 7-23.

Return to Summary Table.

Read and write

Figure 7-23 VDS Control Register
76543210
SO_LIMVDSDIS_H2_VDSDIS_L2_VDSDIS_H1_VDSDIS_L1_VDS
R/W-0bR/W-111bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-23 VDS Control Field Descriptions
BitFieldTypeDefaultDescription
7SO_LIMR/W0b

0b = Default operation

1b = SO output is voltage-limited to 3.6 V

6-4VDSR/W111b

Sets the VDS(OCP) monitor for each FET

000b = 0.06 V

001b = 0.145 V

010b = 0.17 V

011b = 0.2 V

100b = 0.12 V

101b = 0.24 V

110b = 0.48 V

111b = 0.96 V

3DIS_H2_VDSR/W0b

Disables the VDS monitor on the high-side FET of half-bridge 2 (enabled by default)

2DIS_L2_VDSR/W0b

Disables the VDS monitor on the low-side FET of half-bridge 2 (enabled by default)

1DIS_H1_VDSR/W0b

Disables the VDS monitor on the high-side FET of half-bridge 1 (enabled by default)

0DIS_L1_VDSR/W0b

Disables the VDS monitor on the low-side FET of half-bridge 1 (enabled by default)

7.6.8 Config Control Register Name (address = 0x05h)

Config control is shown in Figure 7-24 and described in Table 7-24.

Return to Summary Table.

Read and write

Figure 7-24 Config Control Register
76543210
TOFFCHOP_IDSVREF_SCLSH_ENGAIN_CS
R/W-00bR/W-0bR/W-00bR/W-0bR/W-01b
Table 7-24 Config Control Field Descriptions
BitFieldTypeDefaultDescription
7-6TOFFR/W00b

Off time for PWM current chopping

00b = 25 µs

01b = 50 µs

10b = 100 µs

11b = 200 µs

5CHOP_IDSR/W0b

Disables current regulation (enabled by default)

4-3VREF_SCLR/W00b

Scale factor for the VREF input

00b = 100%

01b = 75%

10b = 50%

11b = 25%

2SH_ENR/W0b

Enables sample and hold operation of the shunt amplifier (disabled by default)

1-0GAIN_CSR/W01b

Shunt amplifier gain setting

00b = 10 V/V

01b = 19.8 V/V

10b = 39.4 V/V

11b = 78 V/V