JAJSCQ3E October   2016  – January 2021 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8.     15
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
サーマルパッド・メカニカル・データ
発注情報

Pin Functions

PINTYPE(1)DESCRIPTION
NAMENO.
DRV8702-Q1DRV8703-Q1
AVDD1414PWRAnalog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to ground with a 6.3-V, 1-µF ceramic capacitor.
CPH3030PWRCharge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins.
CPL3131PWRCharge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins.
DVDD1212PWRLogic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this pin to ground with a 6.3-V, 1-µF ceramic capacitor.
GH11818OHigh-side gate. Connect this pin to the high-side FET gate.
GH22626OHigh-side gate. Connect this pin to the high-side FET gate.
GL12020OLow-side gate. Connect this pin to the low-side FET gate.
GL22424OLow-side gate. Connect this pin to the low-side FET gate.
GND11PWRDevice ground. Connect this pin to the system ground.
GND1313PWRDevice ground. Connect this pin to the system ground.
GND1717PWRDevice ground. Connect this pin to the system ground.
GND4—PWRDevice ground. Connect this pin to the system ground.
GND7—PWRDevice ground. Connect this pin to the system ground.
GND9—PWRDevice ground. Connect this pin to the system ground.
IDRIVE5—ICurrent setting pin for the gate drive. The resistor value or voltage forced on this pin sets the gate-drive current. For more information see the Section 8.2.2.2 section.
IN1/PH22IInput control pins. The logic of this pin is dependent on the MODE pin. This pin is connected to an internal pulldown resistor.
IN2/EN33IInput control pins. The logic of this pin is dependent on the MODE pin. This pin is connected to an internal pulldown resistor.
MODE1111IMode control pin. Pull this pin to logic low to use H-bridge operation. Pull this pin to logic high for independent half-bridge operation. This pin is connected to an internal resistor divider. Operation of this pin is latched on power up or when exiting sleep mode. This pin is connected to an internal pullup and pulldown resistors.
NC3232NCNo connect. No internal connection.
SCLK—7ISPI clock. This pin is for the SPI clock signal. This pin is connected to an internal pulldown resistor.
SDI—6ISPI input. This pin is for the SPI input signal. This pin is connected to an internal pulldown resistor.
SDO—4ODSPI output. This pin is for the SPI output signal. This pin is an open-drain output that requires an external pullup resistor.
SH11919IHigh-side source. Connect this pin to the high-side FET source.
SH22525IHigh-side source. Connect this pin to the high-side FET source
SL22323ILow-side source. Connect this pin to the low-side FET source.
SN2222IShunt-amplifier negative input. Connect this pin to the current-sense resistor.
SO1616OShunt-amplifier output. The voltage on this pin is equal to the SP voltage times AV plus an offset. Place no more than 1 nF of capacitance on this pin.
SP2121IShunt-amplifier positive input. Connect this pin to the current-sense resistor.
VCP2929PWRCharge-pump output. Connect a 16-V, 1-µF ceramic capacitor between this pin and the VM pin.
VDRAIN2727IHigh-side FET drain connection. This pin is common for the two H-bridges.
VDS6—IVDS monitor setting pin. The resistor value or voltage forced on this pin sets the VDS monitor threshold. For more information see the Section 8.2.2.3 section.
VM2828PWRPower supply. Connect this pin to the motor supply voltage. Bypass this pin to ground with a 0.1-µF ceramic plus a 10-µF (minimum) capacitor.
VREF1515ICurrent set reference input. The voltage on this pin sets the driver chopping current.
nWDFLT—9ODWatchdog fault indication pin. This pin is pulled logic low when a watchdog fault condition occurs. This pin is an open-drain output that requires an external pullup resistor.
nFAULT1010ODFault indication pin. This pin is pulled logic low when a fault condition occurs. This pin is an open-drain output that requires an external pullup resistor.
nSCS—5ISPI chip select. This pin is the select and enable for SPI. This pin is active low.
nSLEEP88IDevice sleep mode. Pull this pin to logic low to put device into a low-power sleep mode with the FETs in high impedance (Hi-Z). This pin is connected to an internal pulldown resistor.
(1) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output