SLVSC40H June 2013 – May 2020 DRV8711
PRODUCTION DATA.
In PWM mode, if excessive current is detected on the gate drive outputs (which would be indicative of a failed/shorted output FET or PCB fault), the H-bridge experiencing the fault is disabled, the xPDF bit in the STATUS register is set, and the FAULTn pin is driven low. The H-bridge will remain off, and the xPDF bit will remain set until it is written to 0 or the device is reset.
When in indexer mode, both H-bridges are disabled, the xPDF bit in the STATUS register is set, and the FAULTn pin is driven low. The H-bridges will remain off, and the xPDF bit will remain set until it is written to 0 or the device is reset.