SLVSC40H June 2013 – May 2020 DRV8711
PRODUCTION DATA.
An internal power-up reset circuit monitors the voltage applied to the VM pin. If VM falls below the VM undervoltage lockout voltage, the part is reset, as described below for the case of asserting the RESET pin.
If the RESET pin is asserted, all internal logic including the indexer is reset. All registers are returned to their initial default conditions. The power stage will be disabled, and all inputs, including STEP and the serial interface, are ignored when RESET is active.
On exiting reset state, some time (approximately 1 mS) needs to pass before the part is fully functional.
Applying an active low input to the SLEEPn input pin will place the device into a low power state. In sleep mode, the motor driver circuitry is disabled, the gate drive regulator and charge pump are disabled, and all analog circuitry is placed into a low power state. The digital circuitry in the device still operates, so the device registers can still be accessed via the serial interface.
When SLEEPn is active, the RESET pin does not function. SLEEPn must be exited before RESET will take effect. SLEEPn must also be exited to clear the UVLO bit in the status register.
When exiting from sleep mode, some time (approximately 1 mS) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize.