SLVSCH0 April   2014 DRV8824-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Motor Drivers
      2. 8.3.2 Current Regulation
      3. 8.3.3 Blanking Time
      4. 8.3.4 Microstepping Indexer
      5. 8.3.5 nRESET, nENBLE and nSLEEP Operation
      6. 8.3.6 Protection Circuits
        1. 8.3.6.1 Overcurrent Protection (OCP)
        2. 8.3.6.2 Thermal Shutdown (TSD)
        3. 8.3.6.3 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Information
        1. 8.3.7.1 Thermal Protection
        2. 8.3.7.2 Power Dissipation
        3. 8.3.7.3 Heatsinking
    4. 8.4 Device Functional Modes
      1. 8.4.1 Decay Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stepper Motor Speed
        2. 9.2.2.2 Current Regulation
        3. 9.2.2.3 Decay Modes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
VALUE UNIT
VMx Power supply voltage range –0.3 to 47 V
Digital terminal voltage range –0.5 to 7 V
VREF Input voltage –0.3 to 4 V
ISENSEx terminal voltage –0.3 to 0.8 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous motor drive output current(3) 1.6 A
Continuous total power dissipation See Thermal Information table
TJ Operating virtual junction temperature range –40 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –60 150 °C
VESD HBD (human body model), AEC-Q100 Classification H2 2000 V
CDM (charged device model), AEC-Q100 Classification C4B 750

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VM Motor power supply voltage(1) 8.2 45 V
VREF VREF input voltage(2) 1 3.5 V
IV3P3 V3P3OUT load current 1 mA
(1) All VM terminals must be connected to the same supply voltage.
(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.

7.4 Thermal Information

THERMAL METRIC DRV8824-Q1 UNIT
PWP
28 TERMINAL
RθJA Junction-to-ambient thermal resistance(1) 38.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(2) 23.3
RθJB Junction-to-board thermal resistance(3) 21.2
ψJT Junction-to-top characterization parameter(4) 0.8
ψJB Junction-to-board characterization parameter(5) 20.9
RθJC(bot) Junction-to-case (bottom) thermal resistance(6) 2.6
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

over operating free-air temperature range of -40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 5 8 mA
IVMQ VM sleep mode supply current VM = 24 V 10 20 μA
VUVLO VM undervoltage lockout voltage VM rising 7.8 8.2 V
V3P3OUT REGULATOR
V3P3 V3P3OUT voltage IOUT = 0 to 1 mA, VM = 24 V, TJ = 25°C 3.18 3.30 3.45 V
IOUT = 0 to 1 mA 3.10 3.30 3.50
LOGIC-LEVEL INPUTS
VIL Input low voltage 0.6 0.7 V
VIH Input high voltage 2 5.25 V
VHYS Input hysteresis 0.45 V
IIL Input low current VIN = 0 –20 20 μA
IIH Input high current VIN = 3.3 V 100 μA
RPD Internal pulldown resistance nENBL, nRESET, DIR, STEP, MODEx 100 kΩ
nSLEEP 1 MΩ
nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 μA
DECAY INPUT
VIL Input low threshold voltage For slow decay mode 0.8 V
VIH Input high threshold voltage For fast decay mode 2 V
IIN Input current –100 100 µA
RPU Internal pullup resistance 130 kΩ
RPD Internal pulldown resistance 80 kΩ
H-BRIDGE FETS
RDS(ON) HS FET on resistance VM = 24 V, IO = 1 A, TJ = 25°C 0.63 Ω
VM = 24 V, IO = 1 A, TJ = 85°C 0.76 0.90
VM = 24 V, IO = 1 A, TJ = 125°C 0.85 1
RDS(ON) LS FET on resistance VM = 24 V, IO = 1 A, TJ = 25°C 0.65 Ω
VM = 24 V, IO = 1 A, TJ = 85°C 0.78 0.90
VM = 24 V, IO = 1 A, TJ = 125°C 0.85 1
IOFF Off-state leakage current –20 20 μA
MOTOR DRIVER
fPWM Internal PWM frequency 50 kHz
tBLANK Current sense blanking time 3.75 μs
tR Rise time VM = 24 V 100 360 ns
tF Fall time VM = 24 V 80 250 ns
tDEAD Dead time 400 ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level 1.8 5 A
tTSD Thermal shutdown temperature Die temperature 150 160 180 °C
CURRENT CONTROL
IREF xVREF input current xVREF = 3.3 V –3 3 μA
VTRIP xISENSE trip voltage xVREF = 3.3 V, 100% current setting 635 660 685 mV
ΔITRIP Current trip accuracy
(relative to programmed value)		 xVREF = 3.3 V , 5% current setting –25% 25%
xVREF = 3.3 V , 10% - 34% current setting –15% 15%
xVREF = 3.3 V, 38% - 67% current setting –10% 10%
xVREF = 3.3 V, 71% - 100% current setting –5% 5%
AISENSE Current sense amplifier gain Reference only 5 V/V

7.6 Timing Requirements

MIN MAX UNIT
1 fSTEP Step frequency 250 kHz
2 tWH(STEP) Pulse duration, STEP high 1.9 μs
3 tWL(STEP) Pulse duration, STEP low 1.9 μs
4 tSU(STEP) Setup time, command to STEP rising 200 ns
5 tH(STEP) Hold time, command to STEP rising 200 ns
6 tENBL Enable time, nENBL active to STEP 200 ns
7 tWAKE Wakeup time, nSLEEP inactive to STEP 1 ms
timing_lvsa06.gifFigure 1. Timing Diagram

7.7 Typical Characteristics

C001_SLVSCH0.png
Figure 2. IVM vs VM
C003_SLVSCH0.png
Figure 4. RDS(ON) vs VM
C002_SLVSCH0.png
Figure 3. IVMQ vs VM
C004_SLVSCH0.png
Figure 5. RDS(ON) vs Temperature