JAJS504K October   2009  – January 2022 DRV8824

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Current Regulation
      3. 7.3.3 Decay Mode
      4. 7.3.4 Blanking Time
      5. 7.3.5 Microstepping Indexer
      6. 7.3.6 nRESET, nENBL and nSLEEP Operation
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 Overcurrent Protection (OCP)
        2. 7.3.7.2 Thermal Shutdown (TSD)
        3. 7.3.7.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 STEP/DIR Interface
      2. 7.4.2 Microstepping
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
        1.       Power Supply Recommendations
          1. 9.1 Bulk Capacitance
          2. 9.2 Power Supply and Logic Sequencing
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
    4. 9.4 Power Dissipation
    5. 9.5 Heatsinking
  10. 10Device and Documentation Support
    1. 10.1 Community Resources
    2. 10.2 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHD|28
  • PWP|28
サーマルパッド・メカニカル・データ
発注情報

9.1 Layout Guidelines

The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.01 µF rated for VMx. This capacitor should be placed as close to the VMA and VMB pins as possible with a thick trace or ground plane connection to the device GND pin.

The VMA and VMB pins must be bypassed to ground using a bulk capacitor. This component may be an electrolytic. If VMA and VMB are connected to the same board net, a single bulk capacitor is sufficient.

A low-ESR ceramic capacitor must be placed in between the CP1 and CP2 pins. TI recommends a value of
0.01 µF rated for VMA and VMB. Place this component as close to the pins as possible.

A low-ESR ceramic capacitor must be placed in between the VMA and VCP pins. TI recommends a value of
0.1 µF rated for 16 V. Place this component as close to the pins as possible. Also, an optional 1-MΩ resistor may be placed between VCP and VMA to accelerate discharge of the VCP capacitor.

Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin as possible.