JAJS504K
October 2009 – January 2022
DRV8824
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
PWM Motor Drivers
7.3.2
Current Regulation
7.3.3
Decay Mode
7.3.4
Blanking Time
7.3.5
Microstepping Indexer
7.3.6
nRESET, nENBL and nSLEEP Operation
7.3.7
Protection Circuits
7.3.7.1
Overcurrent Protection (OCP)
7.3.7.2
Thermal Shutdown (TSD)
7.3.7.3
Undervoltage Lockout (UVLO)
7.4
Device Functional Modes
7.4.1
STEP/DIR Interface
7.4.2
Microstepping
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Stepper Motor Speed
8.2.2.2
Current Regulation
8.2.2.3
Decay Modes
8.2.3
Application Curves
Power Supply Recommendations
9.1
Bulk Capacitance
9.2
Power Supply and Logic Sequencing
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
9.3
Thermal Considerations
9.4
Power Dissipation
9.5
Heatsinking
10
Device and Documentation Support
10.1
Community Resources
10.2
Trademarks
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RHD|28
PWP|28
サーマルパッド・メカニカル・データ
RHD|28
QFND050K
PWP|28
PPTD156O
発注情報
jajs504k_oa
jajs504k_pm
7.2
Functional Block Diagram