SLVSA73F April   2010  – July 2014 DRV8825

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Motor Drivers
      2. 8.3.2 Current Regulation
      3. 8.3.3 Decay Mode
      4. 8.3.4 Blanking Time
      5. 8.3.5 Microstepping Indexer
      6. 8.3.6 nRESET, nENBL, and nSLEEP Operation
      7. 8.3.7 Protection Circuits
        1. 8.3.7.1 Overcurrent Protection (OCP)
        2. 8.3.7.2 Thermal Shutdown (TSD)
        3. 8.3.7.3 Undervoltage Lockout (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 STEP/DIR Interface
      2. 8.4.2 Microstepping
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stepper Motor Speed
        2. 9.2.2.2 Current Regulation
        3. 9.2.2.3 Decay Modes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supply and Logic Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Protection
      1. 11.3.1 Power Dissipation
      2. 11.3.2 Heatsinking
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
V(VMx) Power supply voltage –0.3 47 V
Power supply ramp rate 1 V/µs
Digital pin voltage –0.5 7 V
V(xVREF) Input voltage –0.3 4 V
ISENSEx pin voltage(4) –0.8 0.8 V
Peak motor drive output current, t < 1 μs Internally limited A
Continuous motor drive output current(3) 0 2.5 A
Continuous total power dissipation See Thermal Information
TJ Operating junction temperature range –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
(4) Transients of ±1 V for less than 25 ns are acceptable

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –60 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2000 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
V(VMx) Motor power supply voltage range(1) 8.2 45 V
V(VREF) VREF input voltage(2) 1 3.5 V
IV3P3 V3P3OUT load current 0 1 mA
(1) All VM pins must be connected to the same supply voltage.
(2) Operational at VREF between 0 to 1 V, but accuracy is degraded.

7.4 Thermal Information

THERMAL METRIC(1) DRV8825 UNIT
PWP
28 PINS
RθJA Junction-to-ambient thermal resistance(2) 31.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 15.9
RθJB Junction-to-board thermal resistance(4) 5.6
ψJT Junction-to-top characterization parameter(5) 0.2
ψJB Junction-to-board characterization parameter(6) 5.5
RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 1.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current V(VMx) = 24 V 5 8 mA
IVMQ VM sleep mode supply current V(VMx) = 24 V 10 20 μA
V3P3OUT REGULATOR
V3P3 V3P3OUT voltage IOUT = 0 to 1 mA 3.2 3.3 3.4 V
LOGIC-LEVEL INPUTS
VIL Input low voltage 0 0.7 V
VIH Input high voltage 2.2 5.25 V
VHYS Input hysteresis 0.3 0.45 0.6 V
IIL Input low current VIN = 0 –20 20 μA
IIH Input high current VIN = 3.3 V 100 μA
RPD Internal pulldown resistance 100 kΩ
nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 μA
DECAY INPUT
VIL Input low threshold voltage For slow decay mode 0.8 V
VIH Input high threshold voltage For fast decay mode 2 V
IIN Input current –40 40 µA
RPU Internal pullup resistance
(to 3.3 V)		 130 kΩ
RPD Internal pulldown resistance 80 kΩ
H-BRIDGE FETS
RDS(ON) HS FET on resistance V(VMx) = 24 V, IO = 1 A, TJ = 25°C 0.2 Ω
V(VMx) = 24 V, IO = 1 A, TJ = 85°C 0.25 0.32
LS FET on resistance V(VMx) = 24 V, IO = 1 A, TJ = 25°C 0.2
V(VMx) = 24 V, IO = 1 A, TJ = 85°C 0.25 0.32
IOFF Off-state leakage current –20 20 μA
MOTOR DRIVER
ƒPWM Internal current control PWM frequency 30 kHz
tBLANK Current sense blanking time 4 μs
tR Rise time 30 200 ns
tF Fall time 30 200 ns
PROTECTION CIRCUITS
VUVLO VM undervoltage lockout voltage V(VMx) rising 7.8 8.2 V
IOCP Overcurrent protection trip level 3 A
tDEG Overcurrent deglitch time 3 µs
tTSD Thermal shutdown temperature Die temperature 150 160 180 °C
CURRENT CONTROL
IREF xVREF input current V(xVREF) = 3.3 V –3 3 μA
VTRIP xISENSE trip voltage V(xVREF) = 3.3 V, 100% current setting 635 660 685 mV
ΔITRIP Current trip accuracy
(relative to programmed value)		 V(xVREF) = 3.3 V, 5% current setting –25% 25%
V(xVREF) = 3.3 V, 10% to 34% current setting –15% 15%
V(xVREF) = 3.3 V, 38% to 67% current setting –10% 10%
V(xVREF) = 3.3 V, 71% to 100% current setting –5% 5%
AISENSE Current sense amplifier gain Reference only 5 V/V

7.6 Timing Requirements

MIN MAX UNIT
1 ƒSTEP Step frequency 250 kHz
2 tWH(STEP) Pulse duration, STEP high 1.9 μs
3 tWL(STEP) Pulse duration, STEP low 1.9 μs
4 tSU(STEP) Setup time, command before STEP rising 650 ns
5 tH(STEP) Hold time, command after STEP rising 650 ns
6 tENBL Enable time, nENBL active to STEP 650 ns
7 tWAKE Wakeup time, nSLEEP inactive high to STEP input accepted 1.7 ms
timing_lvsa06.gifFigure 1. Timing Diagram

7.7 Typical Characteristics

D001_SLVSA73.gif
Figure 2. IVMx vs V(VMx)
D003_SLVSA73.gif
Figure 4. RDS(ON) vs V(VMx)
D002_SLVSA73.gif
Figure 3. IVMxQ vs V(VMx)
D004_SLVSA73.gif
Figure 5. RDS(ON) vs Temperature