JAJSCW8A January   2017  – July 2018 DRV8886

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 rms Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Controlling RREF With an MCU DAC
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Mode 1: Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        2. 7.3.6.2 Mode 2: Mixed Decay for Increasing and Decreasing Current
        3. 7.3.6.3 Mode 3: Slow Decay for Increasing and Decreasing Current
      7. 7.3.7  Blanking Time
      8. 7.3.8  Charge Pump
      9. 7.3.9  Linear Voltage Regulators
      10. 7.3.10 Logic and Multi-Level Pin Diagrams
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
        4. 7.3.11.4 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at TA = -40 to 125°C, VVM = 8 to 37 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD, AVDD)
VVM VM operating voltage 8 37 V
IVM VM operating supply current ENABLE = 1, nSLEEP = 1, No motor load 5 8 mA
IVMQ VM sleep mode supply current nSLEEP = 0; TA = 25°C 20 μA
nSLEEP = 0; TA = 125°C(1) 40
tSLEEP Sleep time nSLEEP = 0 to sleep-mode 50 200 μs
tWAKE Wake-up time nSLEEP = 1 to output transition 0.85 1.5 ms
tON Turn-on time VM > UVLO to output transition 0.85 1.5 ms
VDVDD Internal regulator voltage 0- to 1-mA external load 2.9 3.3 3.6 V
VAVDD Internal regulator voltage No external load 4.5 5 5.5 V
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage VM + 5.5 V
LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, M1)
VIL Input logic-low voltage 0 0.8 V
VIH Input logic-high voltage 1.6 5.3 V
VHYS Input logic hysteresis 200 mV
IIL Input logic-low current VIN = 0 V –1 1 μA
IIH Input logic-high current VIN = 5 V 100 μA
RPD Pulldown resistance To GND 100 kΩ
tPD(1) Propagation delay STEP to current change 1.2 μs
TRI-LEVEL INPUT (M0, TRQ)
VIL Tri-level input logic low voltage 0 0.65 V
VIZ Tri-level input Hi-Z voltage 0.95 1.1 1.25 V
VIH Tri-level input logic high voltage 1.5 5.3 V
IIL Tri-level input logic low current VIN = 0 V –90 μA
IIH Tri-level input logic high current VIN = 5 V 155 μA
RPD Tri-level pulldown resistance VIN = Hi-Z, to GND 65 kΩ
RPU Tri-level pullup resistance VIN = Hi-Z, to DVDD 130 kΩ
QUAD-LEVEL INPUT (DECAY)
VI1 Quad-level input voltage 1 Can set with 1% 5 kΩ to GND 0 0.14 V
VI2 Quad-level input voltage 2 Can set with 1% 15 kΩ to GND 0.24 0.46 V
VI3 Quad-level input voltage 3 Can set with 1% 44.2 kΩ to GND 0.71 1.24 V
VI4 Quad-level input voltage 4 Can set with 1% 133 kΩ to GND 2.12 5.3 V
IO Output current To GND 17 22 27.25 μA
CONTROL OUTPUTS (nFAULT)
VOL Output logic-low voltage IO = 1 mA, RPULLUP = 4.7 kΩ 0.5 V
IOH Output logic-high leakage VO = 5 V, RPULLUP = 4.7 kΩ –1 1 μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON) High-side FET on resistance VM = 24 V, I = 1.4 A, TA = 25°C 290 346 mΩ
RDS(ON) Low-side FET on resistance VM = 24 V, I = 1.4 A, TA = 25°C 260 320 mΩ
tRISE(1) Output rise time 100 ns
tFALL(1) Output fall time 100 ns
tDEAD(1) Output dead time 200 ns
Vd(1) Body diode forward voltage IOUT = 0.5 A 0.7 1 V
PWM CURRENT CONTROL (RREF)
ARREF RREF transimpedance gain 28.1 30 31.9 kAΩ
VRREF RREF voltage RREF = 18 to 132 kΩ 1.18 1.232 1.28 V
tOFF PWM off-time 20 μs
CRREF Equivalent capacitance on RREF 10 pF
tBLANK PWM blanking time IRREF = 2.0 A, 63% to 100% current setting 1.5 µs
IRREF = 2.0 A, 0% to 63% current setting 1
ΔITRIP Current trip accuracy IRREF = 1.5 A, 10% to 20% current setting, 1% reference resistor –15% 15%
IRREF = 1.5 A, 20% to 63% current setting, 1% reference resistor –10% 10%
IRREF = 1.5 A, 71% to 100% current setting, 1% reference resistor –6.25% 6.25%
PROTECTION CIRCUITS
VUVLO VM UVLO VM falling, UVLO report 7 7.8 V
VM rising, UVLO recovery 7.2 8
VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 200 mV
VCPUV Charge pump undervoltage VCP falling; CPUV report VM + 2 V
IOCP Overcurrent protection trip level Current through any FET 3 A
tOCP(1) Overcurrent deglitch time 1.3 1.9 2.8 μs
tRETRY Overcurrent retry time 1 1.6 ms
TTSD(1) Thermal shutdown temperature Die temperature TJ 150 °C
THYS(1) Thermal shutdown hysteresis Die temperature TJ 20 °C
(1) Specified by design and characterization data