JAJSCW8A January   2017  – July 2018 DRV8886

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 rms Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Controlling RREF With an MCU DAC
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Mode 1: Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        2. 7.3.6.2 Mode 2: Mixed Decay for Increasing and Decreasing Current
        3. 7.3.6.3 Mode 3: Slow Decay for Increasing and Decreasing Current
      7. 7.3.7  Blanking Time
      8. 7.3.8  Charge Pump
      9. 7.3.9  Linear Voltage Regulators
      10. 7.3.10 Logic and Multi-Level Pin Diagrams
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
        4. 7.3.11.4 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Device Functional Modes

The DRV8886 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled, the H-bridge MOSFETs are disabled Hi-Z, and the regulators are disabled.

NOTE

The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8886 device is brought out of sleep mode automatically if nSLEEP is brought logic high.

The tWAKE time must elapse before the outputs change state after wake-up.

TI recommends to keep the STEP pin logic low when coming out of nSLEEP or when applying power.

If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the internal logic is still active. A rising edge on STEP advances the indexer, but the outputs do not change state until the ENABLE pin is asserted.

Table 9 lists a summary of the functional modes.

Table 9. Functional Modes Summary

CONDITION H-BRIDGE CHARGE PUMP INDEXER DVDD AVDD
Operating 8 V < VM < 40 V
nSLEEP pin = 1
ENABLE pin = 1		 Operating Operating Operating Operating Operating
Disabled 8 V < VM < 40 V
nSLEEP pin = 1
ENABLE pin = 0		 Disabled Operating Operating Operating Operating
Sleep mode 8 V < VM < 40
nSLEEP pin = 0		 Disabled Disabled Disabled Disabled Disabled
Fault encountered VM undervoltage (UVLO) Disabled Disabled Disabled Operating Disabled
VCP undervoltage (CPUV) Disabled Operating Operating Operating Operating
Overcurrent (OCP) Disabled Operating Operating Operating Operating
Thermal Shutdown (TSD) Disabled Operating Operating Operating Operating