JAJSGV8B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The operation control 3 register is shown in Figure 78 and described in Table 31.
Register access type: Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB12_HS_EN | HB12_LS_EN | HB11_HS_EN | HB11_LS_EN | HB10_HS_EN | HB10_LS_EN | HB9_HS_EN | HB9_LS_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | HB12_HS_EN | R/W | 0b |
0b = Half-bridge 12 high-side switch is disabled 1b = Half-bridge 12 high-side switch is enabled |
6 | HB12_LS_EN | R/W | 0b |
0b = Half-bridge 12 low-side switch is disabled 1b = Half-bridge 12 low-side switch is enabled |
5 | HB11_HS_EN | R/W | 0b |
0b = Half-bridge 11 high-side switch is disabled 1b = Half-bridge 11 high-side switch is enabled |
4 | HB11_LS_EN | R/W | 0b |
0b = Half-bridge 11 low-side switch is disabled 1b = Half-bridge 11 low-side switch is enabled |
3 | HB10_HS_EN | R/W | 0b |
0b = Half-bridge 10 high-side switch is disabled 1b = Half-bridge 10 high-side switch is enabled |
2 | HB10_LS_EN | R/W | 0b |
0b = Half-bridge 10 low-side switch is disabled 1b = Half-bridge 10 low-side switch is enabled |
1 | HB9_HS_EN | R/W | 0b |
0b = Half-bridge 9 high-side switch is disabled 1b = Half-bridge 9 high-side switch is enabled |
0 | HB9_LS_EN | R/W | 0b |
0b = Half-bridge 9 low-side switch is disabled 1b = Half-bridge 9 low-side switch is enabled |