The DS100BR111A is an extremely low power, high performance repeater designed to support serial links with data rates up to 10.3 Gbps. The DS100BR111A pinout is configured as one bidirectional lane (one transmit, one receive channel). The DS100BR111A inputs feature a powerful 4-stage continuous time linear equalizer (CTLE) to provide a boost of up to +36 dB at 5 GHz and open an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect mediums such as board traces or twin-axial copper cables. The transmitter features a programmable output de-emphasis driver with up to -12 dB and can drive output voltage levels from 600 mVp-p to 1200 mVp-p.
The programmable settings can be applied via pin control, SMBus protocol, or an external EEPROM. In the EEPROM mode, the configuration information is automatically loaded on power up, thereby eliminating the need for an external microprocessor or software driver. The DS100BR111A consumes just 65 mW/channel (typical), and allows the option to turn off unused channels. This ultra low power consumption eliminates the need for external heat sinks and simplifies thermal management in active cable applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DS100BR111A | WQFN (24) | 4.00 mm x 4.00 mm |
Changes from C Revision (April 2013) to D Revision
PIN | I/O, TYPE | DESCRIPTION | ||
---|---|---|---|---|
NAME | NUMBER | |||
DIFFERENTIAL HIGH SPEED I/O's | ||||
INA+, INA- , INB+, INB- |
24, 23 11, 12 |
I, CML | Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination resistors connect both INx+ and INx- to VDD. Compatible with AC coupled CML inputs. | |
OUTA+, OUTA-, OUTB+, OUTB- |
7, 8 20, 19 |
O, CML | Inverting and non-inverting 50 Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs. | |
CONTROL PINS | ||||
ENSMB | 3 | I, 4-LEVEL, LVCMOS |
System Management Bus (SMBus) Enable Pin High = Register Access SMBus Slave Mode Float = Read External EEPROM (SMBus Master Mode) Tie 1 kΩ to GND = Pin Mode |
|
ENSMB = Float or 1 (SMBus MODES) | ||||
SCL | 5 | I, 2-LEVEL, LVCMOS, O, Open Drain |
Clock output when loading EEPROM configuration, reverting to SMBus clock input when EEPROM load is complete (ALL_DONE = 0). External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode) recommended as per SMBus interface standards(2) |
|
SDA | 4 | I, 2-LEVEL, LVCMOS, O, Open Drain |
In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output. External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode) recommended as per SMBus interface standards(2) |
|
AD0-AD3 | 10, 9, 2, 1 | I, 4-LEVEL, LVCMOS |
ENSMB Master or Slave mode SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs. There are 16 addresses supported by these pins. Pins must be tied Low or HIGH when used to define the device SMBus address. (4) |
|
READEN | 17 | I, 2-LEVEL, LVCMOS |
ENSMB = Float: When using SMBus Master Mode, a logic low on this pin starts the load from the external EEPROM. ENSMB = 1: When using SMBus Slave Mode, the VOD_SEL/READEN pin must be tied Low for the AD[3:0] to be active. If this pin is tied High or left floating, an address of 0xB0 will be used for the DS100BR111A. |
|
DONE | 18 | O, 2-LEVEL, LVCMOS |
When using an External EEPROM (ENSMB = Float), Valid Register Load Status Output High = External EEPROM load failed or incomplete Low = External EEPROM load passed |
|
ENSMB = 0 (PIN MODE) | ||||
EQA0, EQA1 EQB0, EQB1 |
10, 9 1, 2 |
I, 4-LEVEL, LVCMOS |
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. EQA[1:0] controls the A channel, and EQB[1:0] controls the B channel. The pins are only active when ENSMB = 0. When ENSMB = 1, the SMBus registers provide independent control of each channel, and the EQB0/B1 pins are converted to SMBus AD2/AD3 inputs. See Table 3 for additional information. |
|
DEMA, DEMB | 4, 5 | I, 4-LEVEL, LVCMOS |
DEMA and DEMB control the level of de-emphasis for the output driver when in 10G mode. DEMA controls the A channel, and DEMB controls the B channel. The pins are only active when ENSMB = 0. When ENSMB = 1, the SMBus registers provide independent control of each channel, and the DEM pins are converted to SMBus SCL and SDA pins. See Table 4 for additional information. |
|
VOD_SEL | 17 | I, 4-LEVEL, LVCMOS |
VOD Select High = (VOD = 950 mVpp or 1150 mVpp) Float = (VOD = 850 mVpp) 20 kΩ to GND = (VOD = 1050 mVpp) 1 kΩ to GND = (VOD = 575 mVpp) See (4)(5) for additional notes. See Table 2 for additional information. |
|
MODE | 18 | I, 4-LEVEL, LVCMOS |
Controls Device Mode of Operation High= 10GbE Mode, Continuous Talk (Output Always On) Float = Slow OOB 20 kΩ to GND = eSATA Mode, Fast OOB, Auto Low Power on 100 µs of inactivity. SD stays active. 1 kΩ to GND = SAS Mode, Fast OOB |
|
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS) | ||||
TX_DIS | 6 | I, 2-LEVEL, LVCMOS |
High = OUTA Enabled, OUTB Disabled Low = OUTA and OUTB Enabled |
|
LOS | 13 | O, Open Drain | Indicates Loss of Signal (Default is LOS on INA). Can be modified via SMBus registers. | |
SD_TH | 14 | I, 4-LEVEL, LVCMOS |
The SD_TH pin controls LOS threshold setting Assert (mVpp), Deassert (mVpp) High = 190 mVpp, 130 mVpp Float = 180 mVpp, 110 mVpp (Default) 20 kΩ to GND = 160 mVpp, 100 mVpp 1 kΩ to GND = 210 mVpp, 150 mVpp(3) |
|
VDD_SEL | 16 | I, FLOAT | Enables the 3.3 V to 2.5 V internal regulator Low = 3.3 V Operation Float = 2.5 V Operation |
|
POWER | ||||
VDD | 21, 22 | Power | Power supply pins When in 2.5 V mode, connect to 2.5 V supply. When in 3.3 V mode, do not connect to any supply voltage. Should be used to attach external decoupling to device, 100 nF recommended. See Power Supply Recommendations for additional information. |
|
VIN | 15 | Power | VIN = 3.3 V ± 10% (input to internal LDO regulator) When in 2.5 V mode, VIN pin must be left floating. See Power Supply Recommendations for additional information. |
|
GND | DAP | Power | Ground pad (DAP - die attach pad). |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage (VDD) | -0.5 | 2.75 | V | |
Supply Voltage (VIN) | -0.5 | 4.0 | V | |
LVCMOS Input/Output Voltage | -0.5 | 4.0 | V | |
CML Input Voltage | -0.5 | (VDD+0.5) | V | |
CML Input Current | -30 | 30 | mA | |
Junction Temperature | 125 | °C | ||
Storage Temperature Range Tstg | -40 | 125 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±5000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1250 |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
Supply Voltage (2.5 V mode) | 2.375 | 2.5 | 2.625 | V |
Supply Voltage (3.3 V mode) | 3.0 | 3.3 | 3.6 | V |
Ambient Temperature | -40 | 25 | +85 | °C |
SMBus (SDA, SCL) | 3.6 | V |
THERMAL METRIC(1) | DS100BR111A | UNIT | |
---|---|---|---|
WQFN/RTW | |||
24 PINS | |||
RθJA | Junction-to-ambient thermal resistance, No Airflow, 4 layer JEDEC | 33 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 3.2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY CURRENT | ||||||
IDD | Supply Current | TX_DIS = Low, EQ = ON VOD_SEL = Float (850 mVpp) |
50 | 63 | mA | |
Auto Low Power Mode TX_DIS = Low, MODE = 20 kΩ VID CHA and CHB = 0.0 V VOD_SEL = Float (850 mVpp) |
12 | 15 | ||||
TX_DIS = HIGH | 25 | 35 | ||||
LVCMOS DC SPECIFICATIONS | ||||||
VIH25 | High Level Input Voltage, 2-Level LVCMOS |
2.5 V Supply Mode | 2.0 | VDD | V | |
VIH33 | High Level Input Voltage, 2-Level LVCMOS |
3.3 V Supply Mode | 2.0 | VIN | V | |
VIL | Low Level Input Voltage, 2-Level LVCMOS |
GND | 0.7 | V | ||
VOH | High Level Output Voltage | IOH = -4.0 mA (3) | 2.0 | V | ||
VOL | Low Level Output Voltage | IOL = 4.0 mA | 0.4 | V | ||
IIN | Input Leakage Current | Vinput = 0 V or VDD VDD_SEL = Float |
-15 | 15 | µA | |
Vinput = 0 V or VIN VDD_SEL = Low |
-15 | 15 | ||||
IIN-P | Input Leakage Current 4-Level Input (1) |
Vinput = 0 V or VDD - 0.05 V VDD_SEL = Float Vinput = 0 V or VIN - 0.05 V VDD_SEL = Low |
-160 | 80 | µA | |
CML RECEIVER INPUTS | ||||||
VTX | Source Transmit Launch Differential Signal Level | Default power-up conditions ENSMB = 0 or 1 |
190 | 800 | 1600 | mVp-p |
RLRX-IN | RX return loss | SDD11 @ 4.1 GHz | -12 | dB | ||
SDD11 @ 11.1 GHz | -8 | |||||
SCD11 @ 11.1 GHz | -10 | |||||
HIGH SPEED TRANSMITTER OUTPUTS | ||||||
VOD1 | Output Voltage Differential Swing | OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Low (575 mVpp setting) DE = Low |
425 | 575 | 725 | mVp-p |
VOD2 | Output Voltage Differential Swing | OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (850 mVpp setting) DE = Low |
675 | 850 | 1025 | |
VOD3 | Output Voltage Differential Swing | OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = 20 kΩ to GND (1050 mVpp) DE = Low |
850 | 1050 | 1275 | |
VOD_DE1 | De-Emphasis Levels | OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (850 mVpp) DE = Float |
-3.5 | dB | ||
VOD_DE2 | De-Emphasis Levels | OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (850 mVpp) DE = 20 kΩ to GND |
-6 | dB | ||
VOD_DE3 | De-Emphasis Levels | OUT+ and OUT- AC coupled and terminated by 50 Ω to GND VOD_SEL = Float (850 mVpp) DE = HIGH |
-9 | dB | ||
VCM-AC | Output Common-Mode Voltage | AC Common Mode Voltage DE = 0 dB, VOD ≤ 1000 mVpp |
4.5 | mV (rms) | ||
VCM-DC | Output DC Common-Mode Voltage | DC Common Mode Voltage | 0 | 1.1 | 1.9 | V |
VIDLE | TX IDLE Output Voltage | VID = 0 mVp-p | 30 | mV | ||
RLTX-DIFF | TX return loss | SDD22 @ 4.1 GHz | -13 | dB | ||
SDD22 @ 11.1 GHz | -9 | |||||
SCC22 @ 2.5 GHz | -22 | |||||
SCC22 @ 11.1 GHz | -10 | |||||
Delta_ZM | Transmitter Termination Mismatch | DC, IFORCE = ± 100 µA (4) | 2.5% | |||
TR/F | Transmitter Rise and Fall Time | Measurement points at 20% - 80% (7) | 38 | ps | ||
TPD | Propagation Delay | Measured at 50% crossing EQ = 0x00 |
230 | ps | ||
TCCSK | Channel to Channel Skew | T = 25°C, VDD = 2.5 V | 7 | ps | ||
TPPSK | Part to Part Skew | T = 25°C, VDD = 2.5 V | 20 | ps | ||
TTX-IDLE-SET-TO-IDLE | Max time to transition to idle after differential signal | VIN = 1 Vpp, 10 Gbps EQ = 0x00, DE = 0 dB |
6.5 | ns | ||
TTX-IDLE-TO-DIFF-DATA | Max time to transition to valid differential signal after idle | VIN = 1 Vpp, 10 Gbps EQ = 0x00, DE = 0 dB |
3.2 | ns | ||
TENV_DISTORT | Active OOB timing distortion, input active time vs. output active time | 3.3 | ns | |||
OUTPUT JITTER SPECIFICATIONS(2) | ||||||
RJ | Random Jitter | No Media Source Amplitude = 700 mVpp, PRBS15 pattern, 10.3125 Gbps VOD = Default, EQ = minimum, DE = 0 dB |
0.3 | ps (rms) | ||
DJ1 | Deterministic Jitter | 0.09 | UI | |||
EQUALIZATION | ||||||
DJE1 | Residual Deterministic Jitter | 10.3125 Gbps 8 meter 30AWG Cable on Input Source = 700 mVpp, PRBS15 pattern EQ = 0x2B |
0.23 | UI | ||
DJE2 | Residual Deterministic Jitter | 10.3125 Gbps 30" 4-mil FR4 on Inputs Source = 700 mVpp, PRBS15 pattern EQ = 0x17 |
0.15 | UI | ||
DE-EMPHASIS | ||||||
DJD1 | Residual Deterministic Jitter | 10.3125 Gbps 10” 4 mil stripline FR4 on Outputs Source = 700 mVpp, PRBS15 pattern EQ = Min, VOD = 1050 mVpp, DE = -3.5 dB |
0.14 | UI |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SERIAL BUS INTERFACE DC SPECIFICATIONS(1) | ||||||
VIL | Data, Clock Input Low Voltage | 0.8 | V | |||
VIH | Data, Clock Input High Voltage | 2.1 | 3.6 | V | ||
IPULLUP | Current Through Pull-Up Resistor or Current Source | High Power Specification | 4 | mA | ||
VDD | Nominal Bus Voltage | 2.375 | 3.6 | V | ||
ILEAK-Bus | Input Leakage Per Bus Segment | See (2) | -200 | 200 | µA | |
CI | Capacitance for SDA and SCL | See (2)(3)(6) | 10 | pF | ||
RTERM | External Termination Resistance pull to VDD = 2.5V ± 5% OR 3.3V ± 10% | Pullup VDD = 3.3 V, See (2)(3)(4) | 2000 | Ω | ||
Pullup VDD = 2.5 V, See (2)(3)(4) | 1000 | Ω | ||||
SERIAL BUS INTERFACE TIMING SPECIFICATIONS | ||||||
FSMB | Bus Operating Frequency | ENSMB = VDD (Slave Mode) | 400 | kHz | ||
ENSMB = Float (Master Mode) (1) | 280 | 400 | 520 | kHz | ||
TBUF | Bus Free Time Between Stop and Start Condition | 1.3 | µs | |||
THD:STA | Hold time after (Repeated) Start Condition. After this period, the first clock is generated. | At IPULLUP, Max | 0.6 | µs | ||
TSU:STA | Repeated Start Condition Setup Time | 0.6 | µs | |||
TSU:STO | Stop Condition Setup Time | 0.6 | µs | |||
THD:DAT | Data Hold Time | 0 | ns | |||
TSU:DAT | Data Setup Time | 100 | ns | |||
TLOW | Clock Low Period | 1.3 | µs | |||
THIGH | Clock High Period | See (5) | 0.6 | 50 | µs | |
tF | Clock/Data Fall Time | See (5) | 300 | ns | ||
tR | Clock/Data Rise Time | See (5) | 300 | ns | ||
tPOR | Time in which a device must be operational after power-on reset | See (6)(5) | 500 | ms |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
TLOS_OFF | Input IDLE to Active RX_LOS response time |
See (5) | 0.035 | µs | ||
TLOS_ON | Input Active to IDLE RX_LOS response time |
See (5) | 0.4 | µs | ||
TOFF | TX Disable assert Time TX_DIS = HIGH to Output OFF |
See (5) | 0.005 | µs | ||
TON | TX Disable negateTime TX_DIS = Low to Output ON |
See (5) | 0.150 | µs | ||
TLP_EXIT | Auto Low Power Exit ALP to Normal Operation |
See (5) | 150 | ns | ||
TLP_ENTER | Auto Low Power Enter Normal Operation to Auto Low Power |
See (5) | 100 | µs |
VOD = 575 mVpp |