SNLS397D October 2011 – April 2015 DS110DF410
PRODUCTION DATA.
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±6000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1250 | |||
Machine model (MM), STD - JESD22-A115-A | ±250 |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
Supply Voltage (VDD to GND) | 2.375 | 2.5 | 2.625 | V |
Ambient Temperature | -40 | 25 | +85 | °C |
THERMAL METRIC(1) | DS110DF410 | UNIT | |
---|---|---|---|
WQFN | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 26.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | — | |
RθJB | Junction-to-board thermal resistance | — | |
ψJT | Junction-to-top characterization parameter | — | |
ψJB | Junction-to-board characterization parameter | — | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER | ||||||
PD | Power Supply Consumption | Average Power Consumption (2) | 720 | mW | ||
Max Transient Power Supply Current (3) | 500 | 610 | mA | |||
NTPS | Supply Noise Tolerance (5) | 50 Hz to 100 Hz | 100 | mVP-P | ||
100 Hz to 10 MHz | 40 | mVP-P | ||||
10 MHz to 5.0 GHz | 10 | mVP-P | ||||
2.5V LVCMOS DC SPECIFICATIONS | ||||||
VIH | High Level Input Voltage | 1.75 | VDD | V | ||
VIH | High level (ADDR[3:0] pins) | 2.28 | VDD | |||
VIL | Low Level Input Voltage | GND | 0.7 | V | ||
VIL | Low Level Input Voltage (ADDR[3:0] pins) | GND | 0.335 | |||
VOH | High Level Output Voltage | IOH = -3mA | 2.0 | V | ||
VOL | Low Level Output Voltage | IOL = 3mA | 0.4 | V | ||
IIN | Input Leakage Current | VIN = VDD | +10 | μA | ||
VIN = GND | -10 | μA | ||||
IIH | Input High Current (EN_SMB pin) | VIN = VDD | +55 | μA | ||
IIL | Input Low Current (EN_SMB pin) | VIN = GND | -110 | μA | ||
3.3V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT) | ||||||
VIH | High Level Input Voltage | VDD = 2.5 V | 1.75 | 3.6 | V | |
VIL | Low Level Input Voltage | VDD = 2.5 V | GND | 0.7 | V | |
VOL | Low Level Output Voltage | IPULLUP = 3mA | 0.4 | V | ||
IIH | Input High Current | VIN = 3.6 V, VDD = 2.5 V | +20 | +40 | μA | |
IIL | Input Low Current | VIN = GND, VDD = 2.5 V | -10 | +10 | μA | |
fSDC | SMBus clock rate | Slave Mode | 100 | 400 | kHz | |
Master Mode(4) | 400 | |||||
DATA BIT RATES | ||||||
RB | Bit Rate Range | 8.5 | 11.3 | Gbps | ||
SIGNAL DETECT | ||||||
SDH | Signal Detect ON Threshold Level | Default differential input signal level to assert signal detect, 10.3125 Gbps, PRBS-31 | 70 | mVp-p | ||
SDL | Signal Detect OFF Threshold Level | Default differential input signal level to de-assert signal detect, 10.3125 Gbps, PRBS-31 | 10 | mVp-p | ||
RECEIVER INPUTS (RXPn, RXNn) | ||||||
VTX2, min | Minimum Source Transmit Launch Signal Level (IN, diff) | See (6) | 600 | mVP-P | ||
VTX2, max | Maximum Source Transmit Launch Signal Level (IN, diff) | See (6) | 1000 | mVP-P | ||
VTX1, max | Maximum Source Transmit Launch Signal Level (IN, diff) | See (7) | 1200 | mVP-P | ||
VTX0, max | Maximum Source Transmit Launch Signal Level (IN, diff) | See (8) | 1600 | mVP-P | ||
LRI | Maximum Differential Input Return Loss - |SDD11| | 100 MHz – 6 GHz(9) | -15 | dB | ||
ZD | Differential Input Impedance | 100 MHz – 6 GHz | 100 | Ω | ||
ZS | Single-ended Input Impedance | 100 MHz – 6 GHz | 50 | Ω | ||
DRIVER OUTPUTS (TXPn, TXNn) | ||||||
VOD0 | Differential output voltage | Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled, SMBus register VOD control (Register 0x2d bits 2:0) set to 0, minimum VOD, De-emphasis control set to minimum (0 dB) | 400 | 675 | mVP-P | |
VOD7 | Differential output voltage | Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled SMBus register VOD control (Register 0x2d bits 2:0) set to 7, maximum VOD De-emphasis control set to minimum (0 dB) | 1000 | mVP-P | ||
VOD_DE | De-emphasis level (11) | Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled Set by SMBus register control to maximum de-emphasis setting, Relative to the nominal 0 dB de-emphasis level set at the minimum de-emphasis setting | -12 | dB | ||
tR, tF | Transition time (rise and fall times)(11)(12) | Transition time control = Full Slew Rate | 39 | ps | ||
Transition time control = Limited Slew Rate | 50 | ps | ||||
LRO | Maximum Differential Output Return Loss - |SDD22| | 100 MHz to 6 GHz (9) | -15 | dB | ||
tDP | Propagation Delay | Retimed data(10) | 300 | ps | ||
TDE | De-emphasis pulse duration(13) | Measured at VOD = 1000 mVP-P, de-emphasis setting = -12 dB | 75 | ps | ||
TJ | Output total jitter | Measured at BER = 10-12(14) | 10 | ps | ||
TSKEW | Intra Pair Skew | Difference in 50% crossing between TXPn and TXNn for any output | 3 | ps | ||
Channel-to-channel skew | 7 | ps | ||||
CLOCK AND DATA RECOVERY | ||||||
BWPLL | PLL Bandwidth -3 dB |
Measured at 10.3125 Gbps | 5 | MHz | ||
JTOL | Input sinusoidal jitter tolerance 10 kHz to 250 MHz sinusoidal jitter frequency |
Measured at BER = 10-15 | 0.6 | UI | ||
JTRANS | Jitter Transfer Sinusoidal jitter at 10 MHz jitter frequency |
Measured at BER = 10-15 | -6 | dB | ||
TLOCK | CDR Lock Time, Ref_mode 3, Fixed Data Rate (eg. 10.3125 Gbps) |
Fixed (manual setting) of CTLE, DFE HEO/VEO lock monitor disabled (register 0x3e, bit 7 set to 0) |
2 | ms | ||
Fixed (manual setting) of CTLE, DFE HEO/VEO lock monitor enabled (register 0x3e, bit 7 set to 1 - default) |
12 | ms | ||||
Medium (20 inch) channel loss with CTLE and DFE adaption, HEO/VEO lock monitor must be enabled(15) |
74 | ms | ||||
TEMPLOCK | CDR Lock, Ref_mode 3, 10.3125 Gbps | Lock Temperature Range tested at -5°C to +85°C | 90 | °C | ||
RECOMMENDED REFERENCE CLOCK SPECS | ||||||
REFf | Input reference clock frequency | 24.9975 | 25 | 25.0025 | MHz | |
RECLK_INPW | Minimum REFCLK_IN Pulse Width | At REFCLK_IN pin | 4 | ns | ||
REFCLK_ OUTDCD | REFCLK_OUT duty cycle distortion | CL = 5 pF | 0.55 | ns | ||
REFVIH | Reference clock input min high threshold | 1.75 | V | |||
REFVIL | Reference clock input max low threshold | 0.7 | V |