SNLS491B July   2014  – February 2015 DS125BR820

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Bus Interface DC Specifications
    7. 6.7 Serial Bus Interface Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Functional Datapath Blocks
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode:
      2. 7.4.2 Slave SMBus Mode:
      3. 7.4.3 SMBus Master Mode
    5. 7.5 Signal Conditioning Settings
    6. 7.6 Programming
      1. 7.6.1 EEPROM Register Map for Single Device
    7. 7.7 Register Maps
      1. 7.7.1 Transfer Of Data Via The SMBus
      2. 7.7.2 SMBus Transactions
      3. 7.7.3 Writing a Register
      4. 7.7.4 Reading a Register
      5. 7.7.5 Detailed Register Map
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Signal Integrity in 40G-CR4/KR4/SAS/SATA/PCIe Applications
      2. 8.1.2 Signal Integrity in 40G-SR4/LR4 Applications
      3. 8.1.3 Rx Detect Functionality in 40G-CR4/KR4/SAS/SATA Applications
    2. 8.2 Typical Applications
      1. 8.2.1 Generic High Speed Repeater
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Front Port Applications (40G-CR4/SR4/LR4)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 PCIe Board Applications (PCIe Gen-3)
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Design Procedure
        3. 8.2.3.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Low 70 mW/Channel (Typ) Power Consumption, with Option to Power Down Unused Channels
  • Seamless Link Training Support
  • Enables Host ASIC to Meet Front-Port Eye Mask Requirements over Longer Reach
  • Advanced Configurable Signal Conditioning I/O
    • Receive CTLE up to 10 dB at 6 GHz
    • Linear Output Driver
    • Variable Output Voltage Range up to 1200 mVp-p
  • Programmable via Pin Selection, EEPROM, or SMBus Interface
  • Single Supply Voltage: 2.5 V or 3.3 V
  • −40°C to 85°C Operating Temperature Range
  • Flow-Thru Layout in 10 mm × 5.5 mm 54-Pin Leadless WQFN Package

2 Applications

  • Front-Port 40G-CR4/SR4/LR4 Link Extension
  • Backplane 40G-KR4 Link Extension
  • SAS/SATA/PCIe Link Extension
  • Other Proprietary High Speed Interfaces up to 12.5 Gbps

Simplified Functional Block Diagram

simplified_schematic.gif

3 Description

The DS125BR820 is an extremely low-power high-performance repeater/redriver designed to support eight channels carrying high speed interface up to 12.5 Gbps, such as 40G-CR4, 40G-KR4, SAS/SATA, and PCIe. The receiver's continuous time linear equalizer (CTLE) provides high frequency boost that is programmable from 3 to 10 dB at 6 GHz (12 Gbps) followed by a linear output driver. The CTLE receiver is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as board traces or twin axial-copper cables. The programmable equalization maximizes the flexibility of physical placement within the interconnect channel and improves overall channel performance.

When operating in 40G-CR4/KR4, SAS/SATA, and PCIe applications, the DS125BR820 preserves transmit signal characteristics, thereby allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency in the link training protocol facilitates system level interoperability and minimizes latency.

The programmable settings can be applied easily via pin control, software (SMBus or I2C), or direct loading from an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, thereby eliminating the need for an external microprocessor or software driver.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS125BR820 WQFN (54) 10 mm × 5.5 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Typical Application Block Diagram

app_diagram.gif