SNLS491B July   2014  – February 2015 DS125BR820

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Bus Interface DC Specifications
    7. 6.7 Serial Bus Interface Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Functional Datapath Blocks
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode:
      2. 7.4.2 Slave SMBus Mode:
      3. 7.4.3 SMBus Master Mode
    5. 7.5 Signal Conditioning Settings
    6. 7.6 Programming
      1. 7.6.1 EEPROM Register Map for Single Device
    7. 7.7 Register Maps
      1. 7.7.1 Transfer Of Data Via The SMBus
      2. 7.7.2 SMBus Transactions
      3. 7.7.3 Writing a Register
      4. 7.7.4 Reading a Register
      5. 7.7.5 Detailed Register Map
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Signal Integrity in 40G-CR4/KR4/SAS/SATA/PCIe Applications
      2. 8.1.2 Signal Integrity in 40G-SR4/LR4 Applications
      3. 8.1.3 Rx Detect Functionality in 40G-CR4/KR4/SAS/SATA Applications
    2. 8.2 Typical Applications
      1. 8.2.1 Generic High Speed Repeater
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Front Port Applications (40G-CR4/SR4/LR4)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 PCIe Board Applications (PCIe Gen-3)
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Design Procedure
        3. 8.2.3.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The CML inputs and outputs have been optimized to work with interconnects using a controlled differential impedance of 100 Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board. To minimize the effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair and intra-pair spacing. See AN-1187 “Leadless Leadframe Package (LLP) Application Report” (literature number SNOA401) for additional information on QFN (WQFN) packages.

10.2 Layout Example

30198710.gifFigure 50. Typical Routing Options

The graphic shown above depicts different transmission line topologies which can be used in various combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by increasing the swell around each hole and by providing for a low inductance return current path. When the via structure is associated with a thick backplane PCB, further optimization such as back drilling is often used to reduce the detrimental high frequency effects of stubs on the signal path.