JAJSK91C August   2018  – June 2021 DS250DF230

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
        1. 8.3.7.1 CDR Bypass (Raw) Mode
        2. 8.3.7.2 CDR Fast Lock Mode
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
        3. 8.3.9.3 Slow Slew Rate
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye-Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-Plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.2 Detailed Design Procedure

The design procedure for front-port applications is as follows:

  1. Determine the total number of channels on the board which require a DS250DF230 for signal conditioning. This will dictate the total number of DS250DF230 devices required for the board. It is generally recommended that channels connected to the same front-port cage be grouped together in the same DS250DF230 device. This will simplify the device settings, as similar loss channels generally use similar settings.
  2. Determine the maximum current draw required for all DS250DF230 retimers. This may impact the selection of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum transient power supply current by the total number of DS250DF230 devices.
  3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two ways to approach this calculation:
    1. Maximum mission-mode operational power consumption is when all channels are locked and re-transmitting the data which is received. PRBS pattern checkers/generators are not used in this mode because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the worst-case power consumption in mission mode by the total number of DS250DF230 devices.
    2. Maximum debug-mode operational power consumption is when all channels are locked and re-transmitting the data which is received. At the same time, some channels’ PRBS checkers or generators may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the total number of DS250DF230 devices.
  4. Determine the SMBus address scheme needed to uniquely address each DS250DF230 device on the board, depending on the total number of devices identified in step 2. Each DS250DF230 can be strapped with one of 16 unique SMBus addresses. If there are more DS250DF230 devices on the board than the number of unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.
  5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus (SMBus Slave Mode).
    1. If SMBus Master Mode will be used, provisions must be made for an EEPROM on the board with 8-bit SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including EEPROM size requirements.
    2. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.
  6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
  7. Make provisions in the schematic and layout for a 30.72 MHz (±100 ppm) or 25 MHz (±100 ppm) single-ended CMOS clock. Each DS250DF230 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5-V CMOS output, then no AC-coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN input. The final retimer’s CAL_CLK_OUT output can be left floating.
  8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that multiple retimers’ INT_N outputs can be connected together because this is an open-drain output. The common INT_N net must be pulled high.
  9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Recommended Operating Conditions, take care to ensure the operating junction temperature is met as well as the CDR stay-in-lock junction temperature range defined in Electrical Characteristics. For example, if initial CDR lock acquisition occurs at an junction temperature of 110°C, then maintaining CDR lock would require the ambient temperature surrounding the DS250DF230 to be kept above (110°C – TEMPLOCK–).