JAJSI56B September   2016  – October 2019 DS280BR820

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics – Serial Management Bus Interface
    7. 6.7 Timing Requirements – Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver Inputs
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Pattern Generator Characteristics
        2. 8.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 8.2.3.3 Equalizing High Pre-Channel Loss
        4. 8.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
        5. 8.2.3.5 Output in FIR Limiting Mode with 16T Pattern
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Stripline Example
      2. 10.2.2 Microstrip Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
Wchannel Power consumption per active channel Channel enabled and in linear mode with maximum driver VOD (DRV_SEL_VOD = 3).
Static power consumption not included.		 82 97 (1) mW
Channel enabled and in linear mode with minimum driver VOD (DRV_SEL_VOD = 0).
Static power consumption not included.		 75 89 (1) mW
Wchannel_FIR Power consumption per active channel Channel enabled and in FIR limiting mode with C0 = 31 and maximum driver VOD (DRV_SEL_VOD = 3).
Static power consumption not included.		 105 123 (1) mW
Channel enabled and in FIR limiting mode with C0 = 31 and minimum driver VOD (DRV_SEL_VOD = 0). Static power consumption not included. 97 115 (1) mW
Wstatic_total Idle (static) mode total device power consumption Channels disabled and powered down
(DRV_PD = 1, EQ_PD = 1).		 110 132 (1) mW
Itotal Active mode total device supply current consumption All channels enabled and in linear mode with maximum driver VOD
(DRV_SEL_VOD = 3).		 307 347 mA
All channels enabled and in linear mode with minimum driver VOD
(DRV_SEL_VOD = 0).		 283 322 mA
Itotal_FIR Active mode total device supply current consumption All channels enabled and in FIR limiting mode with C0 = 31 and maximum driver VOD
(DRV_SEL_VOD = 3).		 380 426 mA
All channels enabled and in FIR limiting mode with C0 = 31 and minimum driver VOD
(DRV_SEL_VOD = 0).		 355 401 mA
Istatic_total Idle (static) mode total device supply current consumption All channels disabled and powered down
(DRV_PD = 1, EQ_PD = 1).		 44 50 mA
LVCMOS DC SPECIFICATIONS (CAL_CLK_IN, CAL_CLK_OUT, READ_EN_N, ALL_DONE_N, TEST[1:0])
VIH High level input voltage 1.75 VDD V
READ_EN_N pin only 1.75 3.6 V
VIL Low level input voltage GND 0.7 V
VOH High level output voltage IOH = 4 mA 2 V
VOL Low level output voltage IOL = –4 mA 0.4 V
IIH Input high leakage current Vinput = VDD, TEST[1:0] pins 16 µA
Vinput = VDD, CAL_CLK_IN pin 66 µA
Vinput = VDD, READ_EN_N pin (2) 1 µA
IIL Input low leakage current Vinput = 0 V, TEST[1:0] pins –38 µA
Vinput = 0 V, CAL_CLK_IN pin (3) –1 µA
Vinput = 0 V, READ_EN_N pin (2) –55 µA
4-LEVEL LOGIC ELECTRICAL SPECIFICATIONS (APPLIES TO 4-LEVEL INPUT CONTROL PINS ADDR0, ADDR1, and EN_SMB)
IIH Input high leakage current 105 µA
IIL Input low leakage current –253 µA
VTH High level (1) input voltage 0.95 × VDD V
Float level input voltage 0.67 × VDD V
10 K to GND input voltage 0.33 × VDD V
Low level (0) input voltage 0.1 V
HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN)
BST CTLE high-frequency boost Measured with maximum CTLE setting and maximum BW setting (EQ_BST1 = 7, EQ_BST2 = 7, EQ_BW = 3). Boost is defined as the gain at 14 GHz relative to 20 MHz. 25.6 dB
Measured with maximum CTLE setting and maximum BW setting (EQ_BST1 = 7, EQ_BST2 = 7, EQ_BW = 3). Boost is defined as the gain at 12.9 GHz relative to 20 MHz. 25.3 dB
BST CTLE high-frequency boost Measured with minimum CTLE setting and minimum BW setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_BW = 0, EQ_EN_BYPASS = 1). Boost is defined as the gain at 14 GHz relative to 20 MHz. 2.4 dB
Measured with minimum CTLE setting and minimum BW setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_BW = 0, EQ_EN_BYPASS = 1). Boost is defined as the gain at 12.9 GHz relative to 20 MHz. 2.4 dB
BSTdelta CTLE high-frequency gain variation Measured with maximum CTLE setting (EQ_BST1 = 7, EQ_BST2 = 7). Gain variation is defined as the total change in gain at 14 GHz due to temperature and voltage variation. < 3 dB
Measured with maximum CTLE setting (EQ_BST1 = 7, EQ_BST2 = 7). Gain variation is defined as the total change in gain at 12.9 GHz due to temperature and voltage variation. < 3 dB
BSTdelta CTLE high-frequency gain variation Measured with minimum CTLE setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_EN_BYPASS = 1). Gain variation is defined as the total change in gain at 14 GHz due to temperature and voltage variation. < 2 dB
Measured with minimum CTLE setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_EN_BYPASS = 1). Gain variation is defined as the total change in gain at 12.9 GHz due to temperature and voltage variation. < 2 dB
RLSDD11 Input differential return loss 50 MHz to 3.7 GHz < -14 dB
3.7 GHz to 10 GHz < -12 dB
10 GHz to 14.1 GHz < -8 dB
14.1 GHz to 20 GHz < -6 dB
RLSDC11 Input differential-to-common-mode return loss 100 MHz to 3.3 GHz < -35 dB
3.3 GHz to 12.9 GHz < -26 dB
12.9 GHz to 20 GHz < -22 dB
RLSCC11 Input common-mode return loss 100 MHz to 10 GHz < -7 dB
10 GHz to 20 GHz < -8 dB
VSDAT AC signal detect assert (ON) differential voltage threshold level Minimum input peak-to-peak amplitude level at device pins required to assert signal detect. 25.78125 Gbps with PRBS7 pattern and 20 dB loss channel. 196 mVpp
VSDDT AC signal detect de-assert (OFF) differential voltage threshold level Maximum input peak-to-peak amplitude level at device pins which causes signal detect to de-assert. 25.78125 Gbps with PRBS7 pattern and 20 dB loss channel. 147 mVpp
VIDlinear Input amplitude linear range. The maximum VID for which the repeater remains linear, defined as ≤1 dB compression of Vout/Vin. Measured with the highest wide-band gain setting (EQ_HIGH_GAIN = 1, DRV_SEL_VOD = 3). Measured with minimal input channel and minimum EQ using a 1 GHz signal. 850 mVpp
Measured with a mid wide-band gain setting (EQ_HIGH_GAIN = 1, DRV_SEL_VOD = 0). Measured with minimal input channel and minimum EQ using a 1 GHz signal. 900 mVpp
Measured with a mid wide-band gain setting (EQ_HIGH_GAIN = 0, DRV_SEL_VOD = 3). Measured with minimal input channel and minimum EQ using a 1 GHz signal. 1050 mVpp
Measured with the lowest wide-band gain setting (EQ_HIGH_GAIN = 0, DRV_SEL_VOD = 0). Measured with minimal input channel and minimum EQ using a 1 GHz signal. 1250 mVpp
HIGH-SPEED DIFFERENTIAL OUTPUTS (TXnP, TXnN)
PREDEM-MAX Maximum pre-cursor de-emphasis in FIR limiting mode Measured with an 16T pattern at 28.125 Gbps using C(0), Reg_0x0B[4:0], set to 0x0C, C(-1), Reg_0x0D[3:0], set to 0xF, and C(+1), Reg_0x0C[3:0], set to 0x0. TX drv_sel_fir, Reg_0x06[0], set to 0x1. -11 dB
PSTDEM-MAX Maximum post-cursor de-emphasis in FIR limiting mode Measured with an 16T pattern at 28.125 Gbps using C(0), Reg_0x0B[4:0], set to 0x0C, C(-1), Reg_0x0D[3:0], set to 0x0, and C(+1), Reg_0x0C[3:0], set to 0xF. TX drv_sel_fir, Reg_0x06[0], set to 0x1. -11 dB
TPRE Pre-cursor FIR tap delay in FIR limiting mode Independent of data rate 28 ps
TPST Post-cursor FIR tap delay in FIR limiting mode Independent of data rate 25 ps
VODLIM-MIN Minimum differential output amplitude in FIR limiting mode Measured with a 16T pattern at 25.78125 Gbps using C(0), Reg_0x0B[4:0], set to 0x00, C(-1), Reg_0x0D[3:0], set to 0x0, and C(+1), Reg_0x0C[3:0], set to 0x0. TX drv_sel_fir, Reg_0x06[0], set to 0x1. VOD, Reg_0x06[7:6], set to 0x0. 185 mVpp
Measured with a 16T pattern at 25.78125 Gbps using C(0), Reg_0x0B[4:0], set to 0x00, C(-1), Reg_0x0D[3:0], set to 0x0, and C(+1), Reg_0x0C[3:0], set to 0x0. TX drv_sel_fir, Reg_0x06[0], set to 0x1. VOD, Reg_0x06[7:6], set to 0x3. 360 mVpp
VODLIM-MAX Maximum differential output amplitude in FIR limiting mode Measured with a 16T pattern at 25.78125 Gbps using C(0), Reg_0x0B[4:0], set to 0x1F, C(-1), Reg_0x0D[3:0], set to 0x0, and C(+1), Reg_0x0C[3:0], set to 0x0. TX drv_sel_fir, Reg_0x06[0], set to 0x1. VOD, Reg_0x06[7:6], set to 0x0. 705 mVpp
Measured with a 16T pattern at 25.78125 Gbps using C(0), Reg_0x0B[4:0], set to 0x1F, C(-1), Reg_0x0D[3:0], set to 0x0, and C(+1), Reg_0x0C[3:0], set to 0x0. TX drv_sel_fir, Reg_0x06[0], set to 0x1. VOD, Reg_0x06[7:6], set to 0x3. 1260 mVpp
VODidle Differential output amplitude, TX disabled or otherwise muted < 10 mVpp
GDC Vout/Vin wide-band amplitude gain in linear mode Measured with the highest wide-band gain setting (EQ_HIGH_GAIN = 1, DRV_SEL_VOD = 3) at 20 MHz. 4.5 dB
Measured with the lowest wide-band gain setting (EQ_HIGH_GAIN = 0, DRV_SEL_VOD = 0) at 20 MHz. –5
Vcm-TX-AC Common-mode AC output noise Defined as (TXP + TXN)/2. Measured with a low-pass filter with 3-dB bandwidth at 33 GHz. 6 mV, RMS
Vcm-TX-DC Common-mode DC output Defined as (TXP + TXN)/2. Measured with a DC signal. 0.75 0.96 1.05 V
RJADD-RMS Additive random jitter Measured single-endedly on a Keysight E5505A phase noise measurement solution with a 28-Gbps 1010 pattern, from 2 kHz to 20 MHz. 11 fs RMS
RLSDD22 Output differential-to-differential return loss 50 MHz to 4.8 GHz < –16 dB
4.8 GHz to 10 GHz < –15
10 GHz to 14.1 GHz < –8
14.1 GHz to 20 GHz < –8
RLSCD22 Output common-mode-to-differential return loss 50 MHz to 6.0 GHz < –21 dB
6.0 GHz to 12.9 GHz < –22
12.9 GHz to 14.1 GHz < –21
14.1 GHz to 20 GHz < –20
RLSCC22 Output common-mode return loss 50 MHz to 3.3 GHz < –13 dB
3.3 GHz to 10.3 GHz < –11
10.3 GHz to 20 GHz < –9
tr, tf Transition time (20%-80%) in FIR limiting mode Measured at 28.125 Gbps with 16T data pattern using C(0), Reg_0x0B[4:0], set to 0x00, C(-1), Reg_0x0D[3:0], set to 0x0, and C(+1), Reg_0x0C[3:0], set to 0x0. TX drv_sel_fir, Reg_0x06[0], set to 0x1. 19.9 ps
Measured at 28.125 Gbps with 16T data pattern using C(0), Reg_0x0B[4:0], set to 0x1F, C(-1), Reg_0x0D[3:0], set to 0x0, and C(+1), Reg_0x0C[3:0], set to 0x0. TX drv_sel_fir, Reg_0x06[0], set to 0x1. 25.8 ps
OTHER PARAMETERS
tD Input-to-output latency (propagation delay) through a channel Linear mode 100 ps
tD Input-to-output latency (propagation delay) through a channel FIR limiting mode, Reg_0x06[0]=1 160 ps
tSK Channel-to-channel interpair skew Latency difference between channels. <14 ps
TEEPROM EEPROM configuration load time Time to assert ALL_DONE_N after REAN_EN_N has been asserted. Single device reading its configuration from an EEPROM with common channel configuration. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time. 4 ms
Time to assert ALL_DONE_N after REAN_EN_N has been asserted. Single device reading its configuration from an EEPROM. Non-common channel configuration. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time. 7
TPOR Power-on reset assertion time Internal power-on reset (PoR) stretch between stable power supply and de-assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted once PoR completes. 60 ms
(1) Max values assume VDD = 2.5 V + 5%.
(2) This pin has an internal weak pull-up.
(3) This pin has an internal weak pull-down.