JAJSI56B September   2016  – October 2019 DS280BR820

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics – Serial Management Bus Interface
    7. 6.7 Timing Requirements – Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver Inputs
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Pattern Generator Characteristics
        2. 8.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 8.2.3.3 Equalizing High Pre-Channel Loss
        4. 8.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
        5. 8.2.3.5 Output in FIR Limiting Mode with 16T Pattern
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Stripline Example
      2. 10.2.2 Microstrip Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)

To configure the DS280BR820 for SMBus master mode, leave the EN_SMB pin floating (no connect). If the DS280BR820 is configured for SMBus master mode, it will remain in the SMBus IDLE state until the READ_EN_N pin is asserted to LOW. Once the READ_EN_N pin is driven LOW, the DS280BR820 becomes an SMBus master and attempts to self-configure by reading device settings stored in an external EEPROM (SMBus 8-bit address 0xA0). When the DS280BR820 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW and then change from an SMBus master to an SMBus slave. Not all bits in the register map can be configured through an EEPROM load. Refer to the Programming Guide for more information.

When designing a system for using the external EEPROM, the user must follow these specific guidelines:

  • Maximum EEPROM size is 8 kb (1024 x 8-bit)
  • Set EN_SMB = FLOAT, configure for SMBus master mode
  • The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 2.5-V or 3.3-V supply.
  • Configure the ADDR[1:0] inputs to select the SMBus slave address for the DS280BR820. Once the DS280BR820 completes its EEPROM load the device becomes a slave on the control bus.

DS280BR820 EEPROM_Daisy_Chain.gifFigure 5. Example Daisy Chain for Multiple Device Single EEPROM Configuration

When tying multiple DS280BR820 devices to the SDA and SDC bus, use these guidelines to configure the devices for SMBus master mode:

  • Use SMBus ADDR[1:0] address bits so that each device can load its configuration from the EEPROM. The example below is for four devices. The first device in the sequence conventionally uses the 8-bit slave write address 0x30, while subsequent devices follow the address order listed below.
    • DS280BR820 instance 1 (U1): ADDR[1:0] = {0, 0} = 0x30
    • DS280BR820 instance 2 (U2): ADDR[1:0] = {0, R} = 0x32
    • DS280BR820 instance 3 (U3): ADDR[1:0] = {0, F} = 0x34
    • DS280BR820 instance 4 (U4): ADDR[1:0] = {0, 1} = 0x36
  • Use a pull-up resistor on SDA and SDC; resistor value = 2 kΩ to 5 kΩ is adequate.
  • Float (no connect) the EN_SMB pin (E3) on all DS280BR820 devices to configure them for SMBus master mode. The EN_SMB pin should not be dynamically changed between the high and float states.
  • Daisy-chain READ_EN_N (pin F13) and ALL_DONE_N (pin D3) from one device to the next device in the following sequence so that they do not compete for master control of the EEPROM at the same time.
    1. Tie READ_EN_N of the first device in the chain (U1) to GND to trigger EEPROM read immediately after the DS280BR820 power-on reset (PoR) completes. Alternatively, drive the READ_EN_N pin from a control device (micro-controller or FPGA) to trigger the EEPROM read at a specific time.
    2. Tie ALL_DONE_N of U1 to READ_EN_N of U2
    3. Tie ALL_DONE_N of U2 to READ_EN_N of U3
    4. Tie ALL_DONE_N of U3 to READ_EN_N of U4
    5. Optional: Tie ALL_DONE_N output of U4 to a micro-controller or an LED to show the devices have been loaded successfully.

Once the ALL_DONE_N status pin of the last device is flagged to indicate that all devices sharing the SMBus line have been successfully programmed, control of the SMBus line is released by the DS280BR820. The device then reverts back to SMBus slave mode. At this point, an external MCU can perform any additional Read or Write operations to the DS280BR820.

Refer to the Programming Guide for additional information concerning SMBus master mode.