JAJSI56B September   2016  – October 2019 DS280BR820

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics – Serial Management Bus Interface
    7. 6.7 Timing Requirements – Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver Inputs
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Pattern Generator Characteristics
        2. 8.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 8.2.3.3 Equalizing High Pre-Channel Loss
        4. 8.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
        5. 8.2.3.5 Output in FIR Limiting Mode with 16T Pattern
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Stripline Example
      2. 10.2.2 Microstrip Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.2 Detailed Design Procedure

The design procedure for backplane and mid-plane applications is as follows:

  1. Determine the total number of channels on the board which require a DS280BR820 for signal conditioning. This will dictate the total number of DS280BR820 devices required. It is generally recommended that channels with similar total insertion loss on the board be grouped together in the same DS280BR820 device. This will simplify the device settings, as similar loss channels generally utilize similar settings.
  2. Determine the maximum current draw required for all DS280BR820 devices. This may impact the selection of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum power supply current by the total number of DS280BR820 devices.
  3. Determine the SMBus address scheme needed to uniquely address each DS280BR820 device on the board, depending on the total number of devices identified in step 1. Each DS280BR820 can be strapped with one of 16 unique SMBus addresses. If there are more DS280BR820 devices on the board than the number of unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of I2C/SMBus switches and multiplexers to split the SMBus into multiple busses.
  4. Determine if the device will be configured from EEPROM (SMBus master mode) or from the system SMBus (SMBus slave mode).
    1. If SMBus master mode will be used, provisions should be made for an EEPROM on the board with 8-bit SMBus address 0xA0.
    2. If SMBus slave mode will be used for all device configurations, an EEPROM is not needed.
  5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD supply and GND. Refer to Power Supply Recommendations for more information.
  6. If there is a need to potentially upgrade to a pin-compatible TI Retimer device, then make provisions in the schematic and layout for a 25-MHz (±100 ppm) single-ended CMOS clock. Each DS280BR820 buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the CAL_CLK_OUT pin. This allows multiple (up to 20) DS280BR820 calibration clocks to be daisy chained to avoid the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5 V CMOS output, then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or resistor ladder is needed between one DS280BR820 CAL_CLK_OUT output and the next DS280BR820’s CAL_CLK_IN input. The final DS280BR820’s CAL_CLK_OUT output can be left floating. A 25 MHz clock is not required for the DS280BR820, but it is good practice to provision for it in case there is a future plan to upgrade to a pin-compatible TI Retimer device.
  7. If there is a need to potentially upgrade to a pin-compatible TI Retimer device, then connect the INT_N pin to an FPGA or CPU for interrupt monitoring. Note that multiple INT_N outputs can be connected together. The common INT_N net should be pulled high to 2.5 V or 3.3 V. The INT_N pin on the DS280BR820 does not perform the interrupt functionality that the equivalent pin on the pin-compatible Retimer device does; however, it is good practice to provision for this in case there is a future plan to upgrade to a pin-compatible TI Retimer device.