JAJSJZ3 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. 8 Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Pin Configurations for Lanes

The DS320PR1601 has 16 data lanes with 16-Tx channels and 16-Rx channels. The data channels are grouped for I2C configurations and PCIe state machine grouping as provided in Table 8-1 using xADDRx and PDx pins. Table 8-1 provides the channel grouping.

GUID-20210330-CA0I-2FJ3-HJVZ-0MK3XLFMLSCT-low.svg Figure 8-1 Pin Configurations for Lanes
Table 8-1 Definition of PDx and xADDRx pins
Pin Name Description

PD_15-12

PD_11-8

PD_7-4

PD_3-0

Active in all device control modes. The pin has internal 1-MΩ weak pulldown resistor. The pin triggers PCIe Rx detect state machine when toggled.

  • High: power down
  • Low: power up normal operation.

Each PD pin sets control for a bank of 8 lanes (4 from Side A and 4 from Side B) to provide flexibility for x4 and x8 bifurcation:

  • PD_15-12: channels x15-12, both Side A and B
  • PD_11-8: channels x11-8, both Side A and B
  • PD_7-4: channels x7-4, both Side A and B
  • PD_3-0: channels x3-0, both Side A and B

PCIe hot plug insertion implementation varies from system to system. PDx pins are driven low in a system (for example, by PCIe CEM interface PRSNTx# or fundamental reset PERST# signal with appropriate polarity). For PCIe x16 application all four PD signals can be shorted together.

A_ADDR1_15-8

A_ADDR0_15-8

A_ADDR1_7-0

A_ADDR0_7-0

B_ADDR1_15-8

B_ADDR0_15-8

B_ADDR1_7-0

B_ADDR0_7-0

5-level input pins as implemented by pull-down resistor on the pin as provided in Table 7-3.

These pins are sampled at device power-up only. Sets SMBus / I2C target address as provided in Table 8-2. Each set of ADDR1 and ADDR0 pins defines the addresses for bank of 8 lanes:

  • A_ADDR1_15-8, A_ADDR0_15-8: channels A15-8 of Side A
  • A_ADDR1_7-0, A_ADDR0_7-0: channels A7-0 of Side A
  • B_ADDR1_15-8, B_ADDR0_15-8: channels B15-8 of Side B
  • B_ADDR1_7-0, B_ADDR0_7-0: channels B7-0 of Side B

Figure 8-1 shows how I2C target addresses are accessed for specific lanes.