The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps.
The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device.
Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DS90CR286AT-Q1 | TSSOP (56) | 14.00 mm × 6.10 mm |
Changes from * Revision (November 2015) to A Revision
PIN | I/O , TYPE | PIN DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
RxIN0+, RxIN0-, RxIN1+, RxIN1-, RxIN2+, RxIN2-, RxIN3+, RxIN3- |
10, 9, 12, 11, 16, 15, 20, 19 |
I, LVDS | Positive and negative LVDS differential data inputs. 100 Ω termination resistors should be placed between RxIN+ and RxIN- receiver inputs as close as possible to the receiver pins for proper signaling. |
RxCLKIN+, RxCLKIN- |
18, 17 |
I, LVDS | Positive and negative LVDS differential clock input. 100 Ω termination resistor should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close as possible to the receiver pins for proper signaling. |
RxOUT[27:0] | 7, 6, 5, 3, 2, 1, 55, 54, 53, 51, 50, 49, 47, 46, 45, 43, 42, 41, 39, 38, 37, 35, 34, 33, 32, 30, 29, 27 |
O, LVCMOS | LVCMOS level data outputs. |
RxCLK OUT | 26 | O, LVCMOS | LVCMOS Ievel clock output. The rising edge acts as the data strobe. |
PWR DWN | 25 | I, LVCMOS | LVCMOS level input. When asserted low, the receiver outputs are low. |
VCC | 56, 48, 40, 31 | Power | Power supply pins for LVCMOS outputs. |
GND | 52, 44, 36, 28, 4 |
Power | Ground pins for LVCMOS outputs. |
PLL VCC | 23 | Power | Power supply for PLL. |
PLL GND | 24, 22 | Power | Ground pin for PLL. |
LVDS VCC | 13 | Power | Power supply pin for LVDS inputs. |
LVDS GND | 21, 14, 8 | Power | Ground pins for LVDS inputs. |