8.1 Overview

The DS90LT012AH is a single-channel, low-voltage differential signaling (LVDS) line receiver. It operates from a single power supply that is nominally 3.3 V, but the supply can be as low as 3 V and as high as 3.6 V. The input to the DS90LT012AH is a differential signal complying with the LVDS Standard (TIA/EIA-644), and the output is a 3.3-V LVCMOS/LVTTL signal. The differential input signal operates with a signal level of 340 mV, nominally, at a common-mode voltage of 1.2 V. The differential nature of the inputs provides immunity to common-mode coupled signals that the driven signal may experience. A termination resistor of 100 Ω is intergrated into DS90LT012AH.

LVDS receivers are intended to be primarily used in an point-to-point configuration. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted-pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100 Ω. The intergrated termination resistor converts the driver output (current mode) into a voltage without the need for external termination and is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account.