JAJSKM3A
november 2020 – november 2020
DS90UB633A-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Recommended Serializer Timing For PCLK
6.7
AC Timing Specifications (SCL, SDA) - I2C-Compatible
6.8
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
6.9
Serializer Switching Characteristics
6.10
Timing Diagrams
6.11
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Serial Frame Format
7.3.2
Line Rate Calculations for the DS90UB633A/662
7.3.3
Error Detection
7.3.4
Synchronizing Multiple Cameras
7.3.5
General Purpose I/O (GPIO) Descriptions
7.3.6
LVCMOS V(VDDIO) Option
7.3.7
Pixel Clock Edge Select (TRFB / RRFB)
7.3.8
Power Down
7.4
Device Functional Modes
7.4.1
DS90UB633A/662 Operation With External Oscillator as Reference Clock
7.4.2
DS90UB633A/662 Operation With Pixel Clock From Imager as Reference Clock
7.4.3
MODE Pin on Serializer
7.4.4
Internal Oscillator
7.4.5
Built-In Self Test
7.4.6
BIST Configuration and Status
7.4.7
Sample BIST Sequence
7.5
Programming
7.5.1
Programmable Controller
7.5.2
Description of Bidirectional Control Bus and I2C Modes
7.5.3
I2C Pass-Through
7.5.4
Slave Clock Stretching
7.5.5
IDX Address Decoder on the Serializer
7.5.6
Multiple Device Addressing
7.6
Register Maps
8
Application and Implementation
8.1
Application Information
8.1.1
Power Over Coax
8.1.2
Power-Up Requirements and PDB Pin
8.1.3
AC Coupling
8.1.4
Transmission Media
8.2
Typical Applications
8.2.1
Coax Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
STP Application
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Interconnect Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
12.1
Packaging Information
12.2
Tape and Reel Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTV|32
MPQF166B
サーマルパッド・メカニカル・データ
RTV|32
QFND448B
発注情報
jajskm3a_oa
6.10
Timing Diagrams
Figure 6-1
Bidirectional Control Bus Timing
Figure 6-2
“Worst Case” Test Pattern for Power Consumption
Figure 6-3
Serializer CML Output Load and Transition Times
Figure 6-4
Measurement Setup Serializer CML Output Load and Transition Times
Figure 6-5
Serializer VOD Setup
Figure 6-6
Serializer VOD Diagram
Figure 6-7
Serializer Input Clock Transition Times
Figure 6-8
Serializer Setup/Hold Times
Figure 6-9
Serializer PLL Lock Time
Figure 6-10
Serializer Delay