JAJSMU1 February   2023 DS90UB638-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics CSI-2
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  RX MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Crystal Recommendations
      6. 7.4.6  Receiver Port Control
      7. 7.4.7  LOCK and PASS Status
      8. 7.4.8  Adaptive Equalizer
        1. 7.4.8.1 Adaptive Equalizer Algorithm
        2. 7.4.8.2 AEQ Settings
          1. 7.4.8.2.1 AEQ Start-Up and Initialization
          2. 7.4.8.2.2 AEQ Range
          3. 7.4.8.2.3 AEQ Timing
          4. 7.4.8.2.4 AEQ Threshold
      9. 7.4.9  Channel Monitor Loop-Through Output Driver (CMLOUT)
        1. 7.4.9.1 Code Example for CMLOUT FPD-Link III RX Port 0:
      10. 7.4.10 RX Port Status
        1. 7.4.10.1 RX Parity Status
        2. 7.4.10.2 FPD-Link Decoder Status
        3. 7.4.10.3 RX Port Input Signal Detection
        4. 7.4.10.4 Line Counter
        5. 7.4.10.5 Line Length
      11. 7.4.11 Sensor Status
      12. 7.4.12 GPIO Support
        1. 7.4.12.1 GPIO Input Control and Status
        2. 7.4.12.2 GPIO Output Pin Control
        3.       49
        4. 7.4.12.3 Forward Channel GPIO
        5. 7.4.12.4 Back Channel GPIO
        6. 7.4.12.5 Other GPIO Pin Controls
      13. 7.4.13 Line Valid and Frame Valid Indicators
      14. 7.4.14 CSI-2 Protocol Layer
      15. 7.4.15 CSI-2 Short Packet
      16. 7.4.16 CSI-2 Long Packet
      17. 7.4.17 CSI-2 Data Type Identifier
      18. 7.4.18 Virtual Channel and Context
      19. 7.4.19 CSI-2 Transmitter Frequency
      20. 7.4.20 CSI-2 Replicate Mode
      21. 7.4.21 CSI-2 Transmitter Output Control
      22. 7.4.22 CSI-2 Transmitter Status
      23. 7.4.23 Video Buffers
      24. 7.4.24 CSI-2 Line Count and Line Length
      25. 7.4.25 FrameSync Operation
        1. 7.4.25.1 External FrameSync Control
        2. 7.4.25.2 Internally Generated FrameSync
          1. 7.4.25.2.1 Code Example for Internally Generated FrameSync
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus and Bidirectional Control Channel
        1. 7.5.1.1 Bidirectional Control
        2. 7.5.1.2 Device Address
        3. 7.5.1.3 Basic I2C Serial Bus Operation
      2. 7.5.2  I2C Target Operation
      3. 7.5.3  Remote Target Operation
      4. 7.5.4  Remote Target Addressing
      5. 7.5.5  I2C Controller Proxy
      6. 7.5.6  I2C Controller Proxy Timing
        1. 7.5.6.1 Code Example for Configuring Fast Mode Plus I2C Operation
      7. 7.5.7  Interrupt Support
        1. 7.5.7.1 Code Example to Enable Interrupts
        2. 7.5.7.2 FPD-Link III Receive Port Interrupts
          1. 7.5.7.2.1 Interrupts on Forward Channel GPIO
          2. 7.5.7.2.2 Interrupts on Change in Sensor Status
        3. 7.5.7.3 Code Example to Readback Interrupts
        4. 7.5.7.4 CSI-2 Transmit Port Interrupts
      8. 7.5.8  Error Handling
        1. 7.5.8.1 Receive Frame Threshold
        2. 7.5.8.2 Port PASS Control
      9. 7.5.9  Pattern Generation
        1. 7.5.9.1 Reference Color Bar Pattern
        2. 7.5.9.2 Fixed Color Patterns
        3. 7.5.9.3 Packet Generator Programming
          1. 7.5.9.3.1 Determining Color Bar Size
        4. 7.5.9.4 Code Example for Pattern Generator
      10. 7.5.10 FPD-Link BIST Mode
        1. 7.5.10.1 BIST Operation Through BISTEN Pin
        2. 7.5.10.2 BIST Operation Through Register Control
    6. 7.6 Unique ID
    7. 7.7 Register Maps
      1. 7.7.1   I2C Device ID Register
      2. 7.7.2   Reset Register
      3. 7.7.3   General Configuration Register
      4. 7.7.4   Revision/Mask ID Register
      5. 7.7.5   DEVICE_STS Register
      6. 7.7.6   PAR_ERR_THOLD_HI Register
      7. 7.7.7   PAR_ERR_THOLD_LO Register
      8. 7.7.8   BCC Watchdog Control Register
      9. 7.7.9   I2C Control 1 Register
      10. 7.7.10  I2C Control 2 Register
      11. 7.7.11  SCL High Time Register
      12. 7.7.12  SCL Low Time Register
      13. 7.7.13  RX_PORT_CTL Register
      14. 7.7.14  IO_CTL Register
      15. 7.7.15  GPIO_PIN_STS Register
      16. 7.7.16  GPIO_INPUT_CTL Register
      17. 7.7.17  GPIO0_PIN_CTL Register
      18. 7.7.18  GPIO1_PIN_CTL Register
      19. 7.7.19  GPIO2_PIN_CTL Register
      20. 7.7.20  GPIO3_PIN_CTL Register
      21. 7.7.21  GPIO4_PIN_CTL Register
      22. 7.7.22  GPIO5_PIN_CTL Register
      23. 7.7.23  GPIO6_PIN_CTL Register
      24. 7.7.24  RESERVED Register
      25. 7.7.25  FS_CTL Register
      26. 7.7.26  FS_HIGH_TIME_1 Register
      27. 7.7.27  FS_HIGH_TIME_0 Register
      28. 7.7.28  FS_LOW_TIME_1 Register
      29. 7.7.29  FS_LOW_TIME_0 Register
      30. 7.7.30  MAX_FRM_HI Register
      31. 7.7.31  MAX_FRM_LO Register
      32. 7.7.32  CSI_PLL_CTL Register
      33. 7.7.33  FWD_CTL1 Register
      34. 7.7.34  FWD_CTL2 Register
      35. 7.7.35  FWD_STS Register
      36. 7.7.36  INTERRUPT_CTL Register
      37. 7.7.37  INTERRUPT_STS Register
      38. 7.7.38  RESERVED Register
      39. 7.7.39  CSI_CTL Register
      40. 7.7.40  CSI_CTL2 Register
      41. 7.7.41  CSI_STS Register
      42. 7.7.42  CSI_TX_ICR Register
      43. 7.7.43  CSI_TX_ISR Register
      44. 7.7.44  CSI_TEST_CTL Register
      45. 7.7.45  CSI_TEST_PATT_HI Register
      46. 7.7.46  CSI_TEST_PATT_LO Register
      47. 7.7.47  RESERVED Register
      48. 7.7.48  RESERVED Register
      49. 7.7.49  RESERVED Register
      50. 7.7.50  RESERVED Register
      51. 7.7.51  RESERVED Register
      52. 7.7.52  RESERVED Register
      53. 7.7.53  SFILTER_CFG Register
      54. 7.7.54  AEQ_CTL1 Register
      55. 7.7.55  AEQ_ERR_THOLD Register
      56. 7.7.56  RESERVED Register
      57. 7.7.57  FPD3_CAP Register
      58. 7.7.58  FPD3_PORT_SEL Register
      59. 7.7.59  RX_PORT_STS1 Register
      60. 7.7.60  RX_PORT_STS2 Register
      61. 7.7.61  RX_FREQ_HIGH Register
      62. 7.7.62  RX_FREQ_LOW Register
      63. 7.7.63  SENSOR_STS_0 Register
      64. 7.7.64  SENSOR_STS_1 Register
      65. 7.7.65  SENSOR_STS_2 Register
      66. 7.7.66  SENSOR_STS_3 Register
      67. 7.7.67  RX_PAR_ERR_HI Register
      68. 7.7.68  RX_PAR_ERR_LO Register
      69. 7.7.69  BIST_ERR_COUNT Register
      70. 7.7.70  BCC_CONFIG Register
      71. 7.7.71  DATAPATH_CTL1 Register
      72. 7.7.72  DATAPATH_CTL2 Register
      73. 7.7.73  SER_ID Register
      74. 7.7.74  SER_ALIAS_ID Register
      75. 7.7.75  TargetID[0] Register
      76. 7.7.76  TargetID[1] Register
      77. 7.7.77  TargetID[2] Register
      78. 7.7.78  TargetID[3] Register
      79. 7.7.79  TargetID[4] Register
      80. 7.7.80  TargetID[5] Register
      81. 7.7.81  TargetID[6] Register
      82. 7.7.82  TargetID[7] Register
      83. 7.7.83  TargetAlias[0] Register
      84. 7.7.84  TargetAlias[1] Register
      85. 7.7.85  TargetAlias[2] Register
      86. 7.7.86  TargetAlias[3] Register
      87. 7.7.87  TargetAlias[4] Register
      88. 7.7.88  TargetAlias[5] Register
      89. 7.7.89  TargetAlias[6] Register
      90. 7.7.90  TargetAlias[7] Register
      91. 7.7.91  PORT_CONFIG Register
      92. 7.7.92  BC_GPIO_CTL0 Register
      93. 7.7.93  BC_GPIO_CTL1 Register
      94. 7.7.94  CSI_VC_MAP Register
      95. 7.7.95  LINE_COUNT_HI Register
      96. 7.7.96  LINE_COUNT_LO Register
      97. 7.7.97  LINE_LEN_1 Register
      98. 7.7.98  LINE_LEN_0 Register
      99. 7.7.99  FREQ_DET_CTL Register
      100. 7.7.100 MAILBOX_1 Register
      101. 7.7.101 MAILBOX_2 Register
      102. 7.7.102 CSI_RX_STS Register
      103. 7.7.103 CSI_ERR_COUNTER Register
      104. 7.7.104 PORT_CONFIG2 Register
      105. 7.7.105 PORT_PASS_CTL Register
      106. 7.7.106 SEN_INT_RISE_CTL Register
      107. 7.7.107 SEN_INT_FALL_CTL Register
      108. 7.7.108 RESERVED Register
      109. 7.7.109 REFCLK_FREQ Register
      110. 7.7.110 RESERVED Register
      111. 7.7.111 IND_ACC_CTL Register
      112. 7.7.112 IND_ACC_ADDR Register
      113. 7.7.113 IND_ACC_DATA Register
      114. 7.7.114 BIST Control Register
      115. 7.7.115 RESERVED Register
      116. 7.7.116 RESERVED Register
      117. 7.7.117 RESERVED Register
      118. 7.7.118 RESERVED Register
      119. 7.7.119 MODE_IDX_STS Register
      120. 7.7.120 LINK_ERROR_COUNT Register
      121. 7.7.121 FPD3_ENC_CTL Register
      122. 7.7.122 RESERVED Register
      123. 7.7.123 GPIO_PD_CTL Register
      124. 7.7.124 PORT_DEBUG Register
      125. 7.7.125 AEQ_CTL2 Register
      126. 7.7.126 AEQ_STATUS Register
      127. 7.7.127 ADAPTIVE EQ BYPASS Register
      128. 7.7.128 AEQ_MIN_MAX Register
      129. 7.7.129 RESERVED Register
      130. 7.7.130 RESERVED Register
      131. 7.7.131 PORT_ICR_HI Register
      132. 7.7.132 PORT_ICR_LO Register
      133. 7.7.133 PORT_ISR_HI Register
      134. 7.7.134 PORT_ISR_LO Register
      135. 7.7.135 FC_GPIO_STS Register
      136. 7.7.136 FC_GPIO_ICR Register
      137. 7.7.137 SEN_INT_RISE_STS Register
      138. 7.7.138 SEN_INT_FALL_STS Register
      139. 7.7.139 FPD3_RX_ID0 Register
      140. 7.7.140 FPD3_RX_ID1 Register
      141. 7.7.141 FPD3_RX_ID2 Register
      142. 7.7.142 FPD3_RX_ID3 Register
      143. 7.7.143 FPD3_RX_ID4 Register
      144. 7.7.144 FPD3_RX_ID5 Register
      145. 7.7.145 I2C_RX0_ID Register
      146. 7.7.146 RESERVED Register
      147. 7.7.147 RESERVED Register
      148. 7.7.148 Indirect Access Registers
      149. 7.7.149 249
      150. 7.7.150 Reserved Register
      151. 7.7.151 PGEN_CTL Register
      152. 7.7.152 PGEN_CFG Register
      153. 7.7.153 PGEN_CSI_DI Register
      154. 7.7.154 PGEN_LINE_SIZE1 Register
      155. 7.7.155 PGEN_LINE_SIZE0 Register
      156. 7.7.156 PGEN_BAR_SIZE1 Register
      157. 7.7.157 PGEN_BAR_SIZE0 Register
      158. 7.7.158 PGEN_ACT_LPF1 Register
      159. 7.7.159 PGEN_ACT_LPF0 Register
      160. 7.7.160 PGEN_TOT_LPF1 Register
      161. 7.7.161 PGEN_TOT_LPF0 Register
      162. 7.7.162 PGEN_LINE_PD1 Register
      163. 7.7.163 PGEN_LINE_PD0 Register
      164. 7.7.164 PGEN_VBP Register
      165. 7.7.165 PGEN_VFP Register
      166. 7.7.166 PGEN_COLOR0 Register
      167. 7.7.167 PGEN_COLOR1 Register
      168. 7.7.168 PGEN_COLOR2 Register
      169. 7.7.169 PGEN_COLOR3 Register
      170. 7.7.170 PGEN_COLOR4 Register
      171. 7.7.171 PGEN_COLOR5 Register
      172. 7.7.172 PGEN_COLOR6 Register
      173. 7.7.173 PGEN_COLOR7 Register
      174. 7.7.174 PGEN_COLOR8 Register
      175. 7.7.175 PGEN_COLOR9 Register
      176. 7.7.176 PGEN_COLOR10 Register
      177. 7.7.177 PGEN_COLOR11 Register
      178. 7.7.178 PGEN_COLOR12 Register
      179. 7.7.179 PGEN_COLOR13 Register
      180. 7.7.180 PGEN_COLOR14 Register
      181. 7.7.181 RESERVED Register
      182. 7.7.182 CSI0_TCK_PREP Register
      183. 7.7.183 CSI0_TCK_ZERO Register
      184. 7.7.184 CSI0_TCK_TRAIL Register
      185. 7.7.185 CSI0_TCK_POST Register
      186. 7.7.186 CSI0_THS_PREP Register
      187. 7.7.187 CSI0_THS_ZERO Register
      188. 7.7.188 CSI0_THS_TRAIL Register
      189. 7.7.189 CSI0_THS_EXIT Register
      190. 7.7.190 CSI0_TPLX Register
      191. 7.7.191 291
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 System
      2. 8.1.2 Power-over-Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. Power Supply Recommendations
    1. 9.1 VDD and VDDIO Power Supply
    2. 9.2 Power-Up Sequencing
      1. 9.2.1 PDB Pin
      2. 9.2.2 System Initialization
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
      1. 10.1.1 Ground
      2. 10.1.2 Routing FPD-Link III Signal Traces and PoC Filter
      3. 10.1.3 Routing CSI-2 Signal Traces
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

GUID-20211028-SS0I-T95N-CF0R-Z7D33XL6VBCD-low.svg Figure 5-1 RGZ Package
48-Pin VQFN
Top View
Table 5-1 Pin Functions
PIN I/O
TYPE
DESCRIPTION
NAME NO.
RECEIVE DATA CSI-2 OUTPUT
CSI_CLK0N 11 O RECEIVE DATA OUTPUT: This signal carries data from the FPD-LINK III Deserializer to the processor over CSI-2 interface. Receive data is CSI-2 configured with DPHY outputs as one differential clock lane (CSI_CLK0P/N) and up to four differential data lanes (CSI_D0P/N: CSI_D3P/N) or two clock lanes (CSI_CLK0P/N, CSI_CLK1P/N) and two differential data lanes for each clock. When in replicate mode data lanes CSI_D2P/N and CSI_D3P/N are associated with clock lane CSI_CLK1P/N to provide the replicated output. Leave unused outputs as no connect.
CSI_CLK0P 12
CSI_CLK1N 18
CSI_CLK1P 19
CSI_D0N 13
CSI_D0P 14
CSI_D1N 15
CSI_D1P 16
CSI_D2N 21
CSI_D2P 22
CSI_D3N 23
CSI_D3P 24
CLOCK INTERFACE
XIN/REFCLK 5 S, I Reference clock input or crystal oscillator input. Pin is shared with XIN and REFCLK. Typically REFCLK connected to 23-MHz to 26-MHz reference oscillator output (100 ppm) or XIN configured with external 23-MHz to 26-MHz crystal to XOUT. See Section 7.4.4.
XOUT 4 O Crystal oscillator output: Output Pin for providing crystal oscillator reference. Leave this pin NC when reference clock input is driving XIN/REFCLK.
SYNCHRONIZATION AND GPIO
GPIO0 28 I/O, PD General-Purpose Input/Output: Pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPIOs on the serializer, or they may be configured to be outputs to follow local register settings. At power up, the GPIO are disabled and include a 35-kΩ (typical) pulldown resistor by default. See Section 7.4.12 for programmability. Unused GPIOs can be left open or no connect.
GPIO1 27
GPIO2 26
GPIO4 10
GPIO5 9
GPIO6 8
GPIO3/INTB 25 I/O, OD General-Purpose Input/Output: Pin GPIO3 can be configured as input signals for GPOs on the serializer. Pin 25 is shared with INTB. Pul lup with 4.7 kΩ to V(VDDIO). The programmable input and output pin is an active-low open drain and controlled by the status registers. See Section 7.4.12 for programmability. Unused GPIO can be left open or no connect.
FPD-LINK III INTERFACE
RIN0– 42 I/O Receive Input Channel 0: Differential FPD-Link receiver and bidirectional control back channel output. The IO must be AC-coupled. For applications that use single-ended, coaxial channel, connect RIN0+ with 33nF, AC-coupling capacitor and terminate RIN0– to GND with a 15nF capacitor and 50-Ω resistor. For STP applications, connect both RIN0+ and RIN0– with 33nF, AC-coupling capacitor. If connecting to a DS90UB633A-Q1, please follow the capacitor values suggested in Design Requirements.
RIN0+ 41
I2C PINS
I2C_SCL 2 I/O, OD I2C Serial Clock: Clock line for the bidirectional control bus communication.
An external 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail is recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See Section 7.5.1 for more information.
I2C_SDA 1 I/O, OD I2C Serial Data: Data line for bidirectional control bus communication.
An external 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail is recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See Section 7.5.1 for more information.
CONFIGURATION AND CONTROL PINS1.2
IDX 35 S, PD Input. I2C Serial Control Bus Primary Device ID Address Select.
Once enabled, the voltage at this pin will be sampled to configure the default I2C device address. This pin is typically connected with external pullup resistor to VDD18 and pulldown resistor to GND to create a voltage divider. See Serial Control Bus Addresses for IDX.
MODE 37 S, PD Mode select configuration input to set operating mode based on input voltage level.
This pin is typically connected to voltage divider through an external pullup to VDD18 and pulldown to GND. Table 7-2.
PDB 30 I, PD Power-down inverted Input Pin. This pin is typically connected to processor GPIO with a pulldown resistor. When PDB input is brought HIGH, the device is enabled and internal register and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN with internal 50-kΩ internal pulldown enabled. PDB should remain low until after power supplies are applied and reach minimum required levels. PDB INPUT IS 3.3-V TOLERANT. See Section 9.2 for more information.
PDB = 1.8V, device is enabled (normal operation).
PDB = 0 V, device is powered down.
VDD_SEL 46 S, PD VDD Select: Configuration pin to select internal LDO regulator supply. When VDD_SEL = LOW, internal 1.1V supply mode is selected. Feed 1.8V to VDD18 inputs = 1.8V ±5%. An internal 1.1V regulator will supply the VDD11. VDD11 inputs should be terminated with bypass capacitors. When VDD_SEL = HIGH, external 1.1V supply mode is selected. After 1.8V supply is applied to VDD18 inputs, then apply 1.1V to VDD11 inputs = 1.1 V ±5%. Voltage at VDD11 supply pins must always be less than main voltage applied to VDD18 when using external 1.1V supply. VDD_SEL IS 3.3V TOLERANT.
DIAGNOSTIC PINS
BISTEN 6 S, PD BIST Enable: BISTEN = H, BIST Mode is enabled BISTEN = L, BIST Mode is disabled. If unused, connect BISTEN directly to GND. See Section 7.5.10 for more information.
CMLOUTP 38 O Monitor Loop-Through Driver differential output which supports functional checks. This pin is typically routed to test points and not connected. For monitoring, CMLOUT should be terminated with 100-Ω differential load. See Section 7.4.9 for more information.
CMLOUTN 39
LOCK 48 O LOCK Status: Output Pin for monitoring lock status of FPD-Link III channel that may be used for Link Status. When LOCK = H, the FPD-Link III receiver is locked and the Rx Port is active. When LOCK = L, the receiver is unlocked. See Section 7.4.7 for more information. Leave pin as no connect if unused.
PASS 47 O PASS Output: PASS = H indicates pass conditions are met, and PASS = L indicates that pass conditions are not met. This pin is typically routed to the processor input pin or test point for monitoring. See Section 7.4.7 for more information. For BIST operation, PASS = H indicates that ERROR FREE Transmission is in forward channel operation. PASS = L in BIST operation indicates that one or more errors were detected in the received payload. See Section 7.5.10 for more information. Leave pin as no connect if unused.
POWER AND GROUND
GND DAP G DAP is the large metal contact at the bottom side, located at the center of the QFN package. Connect to the ground plane (GND).
VDD11_CSI 20 D, P When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
Connect to external 1.1-V power rail
Requires a 0.01-μF to GND
VDD11_D 3 D, P When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
Connect to external 1.1-V power rail
Requires a 0.01-μF to GND
VDD11_FPD0 43 D, P When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
Connect to external 1.1-V power rail
Requires a 0.01-μF to GND Requires a 10-μF to GND shared with VDD11_FPD1
See sections Section 9and Section 8.2 for more information
VDD11_FPD1 34 D, P When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
Connect to external 1.1-V power rail
Requires a 0.01-μF to GND Requires a 10-μF to GND shared with VDD11_FPD0
VDD18_CSI 17 P 1.8-V (±5%) Power Supply.
See Section 8.2 for decoupling capacitor requirements.
VDD18_P0
VDD18_P1
45
36
P 1.8-V (±5%) Power Supplies.
See Section 8.2 for decoupling capacitor requirements.
VDD18_FPD0
VDD18_FPD1
40
31
P 1.8-V (±5%) Analog Power Supplies.
See Section 8.2 for decoupling capacitor requirements.
VDDIO 7, 29 P VDDIO voltage supply input. The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to either a 1.8-V or 3.3-V supply rail. When VDDIO is connected to 1.8-V supply, VDDIO must be within ±100 mV of VDD18 to ensure the output timing requirements are met. See Section 8.2 for decoupling capacitor requirements.
OTHER
RES0 44 PD RES0 must be tied to GND for normal operation.
RES1 32, These pins should be left floating.
RES2 33 These pins should be left floating.
The definitions below define the functionality of the I/O cells for each pin. TYPE:
  • I = Input
  • O = Output
  • I/O = Input/Output
  • S = Configuration pin (All strap pins have internal pulldowns. If the default strap value is needed to be changed then use an external resistor.)
  • PD = Internal pulldown
  • OD = Open Drain
  • P, G = Power supply, ground
  • D = Decoupling pin for internal voltage rail