5 Pin Configuration and Functions

Figure 5-1 RGZ Package
48-Pin VQFN
Top View

Table 5-1 Pin Functions

PIN		I/O TYPE	DESCRIPTION
NAME	NO.	I/O TYPE	DESCRIPTION
RECEIVE DATA CSI-2 OUTPUT
CSI_CLK0N	11	O	RECEIVE DATA OUTPUT: This signal carries data from the FPD-LINK III Deserializer to the processor over CSI-2 interface. Receive data is CSI-2 configured with DPHY outputs as one differential clock lane (CSI_CLK0P/N) and up to four differential data lanes (CSI_D0P/N: CSI_D3P/N) or two clock lanes (CSI_CLK0P/N, CSI_CLK1P/N) and two differential data lanes for each clock. When in replicate mode data lanes CSI_D2P/N and CSI_D3P/N are associated with clock lane CSI_CLK1P/N to provide the replicated output. Leave unused outputs as no connect.
CSI_CLK0P	12
CSI_CLK1N	18
CSI_CLK1P	19
CSI_D0N	13
CSI_D0P	14
CSI_D1N	15
CSI_D1P	16
CSI_D2N	21
CSI_D2P	22
CSI_D3N	23
CSI_D3P	24
CLOCK INTERFACE
XIN/REFCLK	5	S, I	Reference clock input or crystal oscillator input. Pin is shared with XIN and REFCLK. Typically REFCLK connected to 23-MHz to 26-MHz reference oscillator output (100 ppm) or XIN configured with external 23-MHz to 26-MHz crystal to XOUT. See Section 7.4.4.
XOUT	4	O	Crystal oscillator output: Output Pin for providing crystal oscillator reference. Leave this pin NC when reference clock input is driving XIN/REFCLK.
SYNCHRONIZATION AND GPIO
GPIO0	28	I/O, PD	General-Purpose Input/Output: Pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPIOs on the serializer, or they may be configured to be outputs to follow local register settings. At power up, the GPIO are disabled and include a 35-kΩ (typical) pulldown resistor by default. See Section 7.4.12 for programmability. Unused GPIOs can be left open or no connect.
GPIO1	27
GPIO2	26
GPIO4	10
GPIO5	9
GPIO6	8
GPIO3/INTB	25	I/O, OD	General-Purpose Input/Output: Pin GPIO3 can be configured as input signals for GPOs on the serializer. Pin 25 is shared with INTB. Pul lup with 4.7 kΩ to V_(VDDIO). The programmable input and output pin is an active-low open drain and controlled by the status registers. See Section 7.4.12 for programmability. Unused GPIO can be left open or no connect.
FPD-LINK III INTERFACE
RIN0–	42	I/O	Receive Input Channel 0: Differential FPD-Link receiver and bidirectional control back channel output. The IO must be AC-coupled. For applications that use single-ended, coaxial channel, connect RIN0+ with 33nF, AC-coupling capacitor and terminate RIN0– to GND with a 15nF capacitor and 50-Ω resistor. For STP applications, connect both RIN0+ and RIN0– with 33nF, AC-coupling capacitor. If connecting to a DS90UB633A-Q1, please follow the capacitor values suggested in Design Requirements.
RIN0+	41	I/O
I2C PINS
I2C_SCL	2	I/O, OD	I2C Serial Clock: Clock line for the bidirectional control bus communication. An external 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail is recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See Section 7.5.1 for more information.
I2C_SDA	1	I/O, OD	I2C Serial Data: Data line for bidirectional control bus communication. An external 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail is recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See Section 7.5.1 for more information.
CONFIGURATION AND CONTROL PINS1.2
IDX	35	S, PD	Input. I2C Serial Control Bus Primary Device ID Address Select. Once enabled, the voltage at this pin will be sampled to configure the default I2C device address. This pin is typically connected with external pullup resistor to VDD18 and pulldown resistor to GND to create a voltage divider. See Serial Control Bus Addresses for IDX.
MODE	37	S, PD	Mode select configuration input to set operating mode based on input voltage level. This pin is typically connected to voltage divider through an external pullup to VDD18 and pulldown to GND. Table 7-2.
PDB	30	I, PD	Power-down inverted Input Pin. This pin is typically connected to processor GPIO with a pulldown resistor. When PDB input is brought HIGH, the device is enabled and internal register and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN with internal 50-kΩ internal pulldown enabled. PDB should remain low until after power supplies are applied and reach minimum required levels. PDB INPUT IS 3.3-V TOLERANT. See Section 9.2 for more information. PDB = 1.8V, device is enabled (normal operation). PDB = 0 V, device is powered down.
VDD_SEL	46	S, PD	VDD Select: Configuration pin to select internal LDO regulator supply. When VDD_SEL = LOW, internal 1.1V supply mode is selected. Feed 1.8V to VDD18 inputs = 1.8V ±5%. An internal 1.1V regulator will supply the VDD11. VDD11 inputs should be terminated with bypass capacitors. When VDD_SEL = HIGH, external 1.1V supply mode is selected. After 1.8V supply is applied to VDD18 inputs, then apply 1.1V to VDD11 inputs = 1.1 V ±5%. Voltage at VDD11 supply pins must always be less than main voltage applied to VDD18 when using external 1.1V supply. VDD_SEL IS 3.3V TOLERANT.
DIAGNOSTIC PINS
BISTEN	6	S, PD	BIST Enable: BISTEN = H, BIST Mode is enabled BISTEN = L, BIST Mode is disabled. If unused, connect BISTEN directly to GND. See Section 7.5.10 for more information.
CMLOUTP	38	O	Monitor Loop-Through Driver differential output which supports functional checks. This pin is typically routed to test points and not connected. For monitoring, CMLOUT should be terminated with 100-Ω differential load. See Section 7.4.9 for more information.
CMLOUTN	39	O
LOCK	48	O	LOCK Status: Output Pin for monitoring lock status of FPD-Link III channel that may be used for Link Status. When LOCK = H, the FPD-Link III receiver is locked and the Rx Port is active. When LOCK = L, the receiver is unlocked. See Section 7.4.7 for more information. Leave pin as no connect if unused.
PASS	47	O	PASS Output: PASS = H indicates pass conditions are met, and PASS = L indicates that pass conditions are not met. This pin is typically routed to the processor input pin or test point for monitoring. See Section 7.4.7 for more information. For BIST operation, PASS = H indicates that ERROR FREE Transmission is in forward channel operation. PASS = L in BIST operation indicates that one or more errors were detected in the received payload. See Section 7.5.10 for more information. Leave pin as no connect if unused.
POWER AND GROUND
GND	DAP	G	DAP is the large metal contact at the bottom side, located at the center of the QFN package. Connect to the ground plane (GND).
VDD11_CSI	20	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF to GND
VDD11_D	3	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF to GND
VDD11_FPD0	43	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF to GND Requires a 10-μF to GND shared with VDD11_FPD1 See sections Section 9and Section 8.2 for more information
VDD11_FPD1	34	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF to GND Requires a 10-μF to GND shared with VDD11_FPD0
VDD18_CSI	17	P	1.8-V (±5%) Power Supply. See Section 8.2 for decoupling capacitor requirements.
VDD18_P0 VDD18_P1	45 36	P	1.8-V (±5%) Power Supplies. See Section 8.2 for decoupling capacitor requirements.
VDD18_FPD0 VDD18_FPD1	40 31	P	1.8-V (±5%) Analog Power Supplies. See Section 8.2 for decoupling capacitor requirements.
VDDIO	7, 29	P	VDDIO voltage supply input. The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to either a 1.8-V or 3.3-V supply rail. When VDDIO is connected to 1.8-V supply, VDDIO must be within ±100 mV of VDD18 to ensure the output timing requirements are met. See Section 8.2 for decoupling capacitor requirements.
OTHER
RES0	44	PD	RES0 must be tied to GND for normal operation.
RES1	32,	—	These pins should be left floating.
RES2	33	—	These pins should be left floating.

The definitions below define the functionality of the I/O cells for each pin. TYPE:

I = Input
O = Output
I/O = Input/Output
S = Configuration pin (All strap pins have internal pulldowns. If the default strap value is needed to be changed then use an external resistor.)
PD = Internal pulldown
OD = Open Drain
P, G = Power supply, ground
D = Decoupling pin for internal voltage rail

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5 Pin Configuration and Functions