JAJSMU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved |
5 | LINK_SFIL_WAIT | RW | 1 | During SFILTER adaption, setting this bit will cause the Lock detect circuit to ignore errors during the SFILTER wait period after the SFILTER control is updated. 1: Errors during SFILTER Wait period will be ignored 0: Errors during SFILTER Wait period will not be ignored and may cause loss of Lock |
4 | LINK_ERR _COUNT_EN | RW | 1 | Enable serial link data integrity error count 1: Enable error count 0: DISABLE |
3:0 | LINK_ERR _THRESH | RW | 0x3 | Link error count threshold. The Link Error Counter monitors the forward channel link and determines when link will be dropped. The link error counter is pixel clock based. FPD Link parity, clock, and control are monitored for link errors. If the error counter is enabled, the deserializer will lose lock once the error counter reaches the LINK_ERR_THRESH value. If the link error counter is disabled, the deserilizer will lose lock after one error. The control bits in DIGITAL_DEBUG_2 register can be used to disable error conditions individually. |