JAJSMU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
The DS90UB638-Q1 seven GPIO pins can output data received from the forward channel when paired with the DS90UB63x-Q1 CSI-2 serializer. The remote Serializer GPIO are mapped to a Deserializer GPIO. Each GPIO pin can be programmed for output mode and mapped. Up to four GPIOs are supported in the forward direction on the FPD-Link III Receive port (see Table 7-87). Each forward channel GPIO can be mapped to any GPIO output pin.
The timing for the forward channel GPIO is dependant on the number of GPIOs assigned at the serializer. When a single GPIO input from the DS90UB63x-Q1 CSI-2 serializer is linked to a DS90UB638-Q1 deserializer, the GPIO output value is sampled every forward channel transmit frame. Two linked GPIO are sampled every two forward channel frames and three or four linked GPIO are sampled every five frames. The typical minimum latency for the GPIO remains consistent (approximately 200 ns), but as the information gets spread over multiple frames, the jitter is typically increased on the order of the sampling period (number of forward channel frames). TI recommends maintaining a 4x over-sampling ratio for linked GPIO throughput. For example, when operating at -Gbps with REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the number of GPIO linked over the forward channel is shown in Table 7-7.
| NUMBER OF LINKED FORWARD CHANNEL GPIOs (FC_GPIO_EN Table 7-87) | SAMPLING FREQUENCY (MHz) AT FPD-Link III LINE RATE = Gbps | MAXIMUM RECOMMENDED FORWARD CHANNEL GPIO FREQUENCY (MHz) | TYPICAL JITTER (ns) |
|---|---|---|---|
| 1 | 121.25 | 30.31 | 12 |
| 2 | 60.63 | 15.15 | 24 |
| 4 | 30.31 | 7.57 | 60 |
In addition to mapping remote serializer GPI, an internally generated FrameSync (see Section 7.4.25) or other control signals may be output from any of the deserializer GPIOs for synchronization with a local processor or another deserializer.