JAJSMU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
RX port specific register dependent on the settings in register 0x4C.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7 | RESERVED | R | 0 | Reserved |
6 | RX_PORT_NUM | R | 0 | RX Port Number. This read-only field indicates the number of the currently selected RX read port. |
5 | BCC_CRC_ERROR | R/COR | 0 | Bi-directional Control Channel CRC Error Detected This bit indicates a CRC error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read. |
4 | LOCK_STS_CHG | R/COR | 0 | Lock Status Changed This bit is set if a change in receiver lock status has been detected since the last read of this register. Current lock status is available in the LOCK_STS bit of this register. This bit is cleared on read. |
3 | BCC_SEQ_ERROR | R/COR | 0 | Bi-directional Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read. |
2 | PARITY_ERROR | R | 0 | FPD-Link III parity errors detected This flag is set when the number of parity errors detected is greater than the threshold programmed in the PAR_ERR_THOLD registers. 1: Number of FPD-Link III parity errors detected is greater than the threshold 0: Number of FPD-Link III parity errors is below the threshold This bit is cleared when the RX_PAR_ERR_HI/LO registers are cleared. |
1 | PORT_PASS | R | 0 | Receiver PASS indication. This bit indicates the current status of the Receiver PASS indication. The requirements for setting the Receiver PASS indication are controlled by the PORT_PASS_CTL register. 1: Receive input has met PASS criteria 0: Receive input does not meet PASS criteria |
0 | LOCK_STS | R | 0 | FPD-Link III receiver is locked to incoming data 1: Receiver is locked to incoming data 0: Receiver is not locked |