JAJSKM4A november   2020  – november 2020 DS90UB662-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 CSI-2 Timing Specifications
    8. 6.8 Recommended Timing for the Serial Control Bus
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Receiver Port Control
        1. 7.4.5.1 Video Stream Forwarding
      6. 7.4.6  Input Jitter Tolerance
      7. 7.4.7  Adaptive Equalizer
        1. 7.4.7.1 Transmission Distance
        2. 7.4.7.2 Adaptive Equalizer Algorithm
        3. 7.4.7.3 AEQ Settings
          1. 7.4.7.3.1 AEQ Start-Up and Initialization
          2. 7.4.7.3.2 AEQ Range
          3. 7.4.7.3.3 AEQ Timing
          4. 7.4.7.3.4 AEQ Threshold
      8. 7.4.8  Channel Monitor Loop-Through Output Driver
        1. 7.4.8.1 Code Example for CMLOUT FPD3 RX Port 0:
      9. 7.4.9  RX Port Status
        1. 7.4.9.1 RX Parity Status
        2. 7.4.9.2 FPD-Link Decoder Status
        3. 7.4.9.3 RX Port Input Signal Detection
        4. 7.4.9.4 Line Counter
        5. 7.4.9.5 Line Length
      10. 7.4.10 Sensor Status
      11. 7.4.11 GPIO Support
        1. 7.4.11.1 GPIO Input Control and Status
        2. 7.4.11.2 GPIO Output Pin Control
        3. 7.4.11.3 Forward Channel GPIO
        4. 7.4.11.4 Back Channel GPIO
        5. 7.4.11.5 GPIO Pin Status
        6. 7.4.11.6 Other GPIO Pin Controls
      12. 7.4.12 RAW Mode LV / FV Controls
      13. 7.4.13 CSI-2 Protocol Layer
      14. 7.4.14 CSI-2 Short Packet
      15. 7.4.15 CSI-2 Long Packet
      16. 7.4.16 CSI-2 Data Identifier
      17. 7.4.17 Virtual Channel and Context
      18. 7.4.18 CSI-2 Mode Virtual Channel Mapping
        1. 7.4.18.1 Example 1
      19. 7.4.19 CSI-2 Transmitter Frequency
      20. 7.4.20 CSI-2 Output Bandwidth
        1. 7.4.20.1 CSI-2 Output Bandwidth Calculation Example
      21. 7.4.21 CSI-2 Transmitter Status
      22. 7.4.22 Video Buffers
      23. 7.4.23 CSI-2 Line Count and Line Length
      24. 7.4.24 FrameSync Operation
        1. 7.4.24.1 External FrameSync Control
        2. 7.4.24.2 Internally Generated FrameSync
          1. 7.4.24.2.1 Code Example for Internally Generated FrameSync
      25. 7.4.25 CSI-2 Forwarding
        1. 7.4.25.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 7.4.25.2 Synchronized CSI-2 Forwarding
        3. 7.4.25.3 Basic Synchronized CSI-2 Forwarding
          1. 7.4.25.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 7.4.25.4 Line-Interleaved CSI-2 Forwarding
          1. 7.4.25.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 7.4.25.5 Line-Concatenated CSI-2 Forwarding
          1. 7.4.25.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 7.4.25.6 CSI-2 Transmitter Output Control
        7. 7.4.25.7 Enabling and Disabling CSI-2 Transmitters
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus
      2. 7.5.2  Second I2C Port
      3. 7.5.3  I2C Slave Operation
      4. 7.5.4  Remote Slave Operation
      5. 7.5.5  Remote Slave Addressing
      6. 7.5.6  Broadcast Write to Remote Devices
        1. 7.5.6.1 Code Example for Broadcast Write
      7. 7.5.7  I2C Master Proxy
      8. 7.5.8  I2C Master Proxy Timing
        1. 7.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 7.5.9  Interrupt Support
        1. 7.5.9.1 Code Example to Enable Interrupts
        2. 7.5.9.2 FPD-Link III Receive Port Interrupts
        3. 7.5.9.3 Interrupts on Forward Channel GPIO
        4. 7.5.9.4 Interrupts on Change in Sensor Status
        5. 7.5.9.5 Code Example to Readback Interrupts
        6. 7.5.9.6 CSI-2 Transmit Port Interrupts
      10. 7.5.10 Error Handling
        1. 7.5.10.1 Receive Frame Threshold
        2. 7.5.10.2 Port PASS Control
      11. 7.5.11 Timestamp – Video Skew Detection
      12. 7.5.12 Pattern Generation
        1. 7.5.12.1 Reference Color Bar Pattern
        2. 7.5.12.2 Fixed Color Patterns
        3. 7.5.12.3 Packet Generator Programming
          1. 7.5.12.3.1 Determining Color Bar Size
        4. 7.5.12.4 Code Example for Pattern Generator
      13. 7.5.13 FPD-Link BIST Mode
        1. 7.5.13.1 BIST Operation
    6. 7.6 Register Maps
      1. 7.6.1  Digital Registers (Shared)
        1. 7.6.1.1  I2C Device ID Register
        2. 7.6.1.2  Reset Control Register
        3. 7.6.1.3  General Configuration Register
        4. 7.6.1.4  Revision / Mask ID Register
        5. 7.6.1.5  Device Status Register
        6. 7.6.1.6  PAR_ERR_THOLD_HI Register
        7. 7.6.1.7  PAR_ERR_THOLD_LO Register
        8. 7.6.1.8  BCC_WATCHDOG_CONTROL Register
        9. 7.6.1.9  I2C_CONTROL_1 Register
        10. 7.6.1.10 I2C_CONTROL_2 Register
        11. 7.6.1.11 SCL High Time Register
        12. 7.6.1.12 SCL Low Time Register
        13. 7.6.1.13 RX_PORT_CTL Register
        14. 7.6.1.14 IO_CTL Register
        15. 7.6.1.15 GPIO_PIN_STS Register
        16. 7.6.1.16 GPIO_INPUT_CTL Register
        17. 7.6.1.17 GPIO0_PIN_CTL Register
        18. 7.6.1.18 GPIO1_PIN_CTL Register
        19. 7.6.1.19 GPIO2_PIN_CTL Register
        20. 7.6.1.20 GPIO3_PIN_CTL Register
        21. 7.6.1.21 GPIO4_PIN_CTL Register
        22. 7.6.1.22 GPIO5_PIN_CTL Register
        23. 7.6.1.23 GPIO6_PIN_CTL Register
        24. 7.6.1.24 GPIO7_PIN_CTL Register
        25. 7.6.1.25 FS_CTL Register
        26. 7.6.1.26 FS_HIGH_TIME_1 Register
        27. 7.6.1.27 FS_HIGH_TIME_0 Register
        28. 7.6.1.28 FS_LOW_TIME_1 Register
        29. 7.6.1.29 FS_LOW_TIME_0 Register
        30. 7.6.1.30 MAX_FRM_HI Register
        31. 7.6.1.31 MAX_FRM_LO Register
        32. 7.6.1.32 CSI_PLL_CTL Register
        33. 7.6.1.33 FWD_CTL1 Register
        34. 7.6.1.34 FWD_CTL2 Register
        35. 7.6.1.35 FWD_STS Register
        36. 7.6.1.36 INTERRUPT_CTL Register
        37. 7.6.1.37 INTERRUPT_STS Register
        38. 7.6.1.38 TS_CONFIG Register
        39. 7.6.1.39 TS_CONTROL Register
        40. 7.6.1.40 TS_LINE_HI Register
        41. 7.6.1.41 TS_LINE_LO Register
        42. 7.6.1.42 TS_STATUS Register
        43. 7.6.1.43 TIMESTAMP_P0_HI Register
        44. 7.6.1.44 TIMESTAMP_P0_LO Register
        45. 7.6.1.45 TIMESTAMP_P1_HI Register
        46. 7.6.1.46 TIMESTAMP_P1_LO Register
        47. 7.6.1.47 TIMESTAMP_P2_HI Register
        48. 7.6.1.48 TIMESTAMP_P2_LO Register
        49. 7.6.1.49 TIMESTAMP_P3_HI Register
        50. 7.6.1.50 TIMESTAMP_P3_LO Register
      2. 7.6.2  CSI-2 Port Select Register
      3. 7.6.3  Digital CSI-2 Registers (Paged)
        1. 7.6.3.1 CSI_CTL Register
        2. 7.6.3.2 CSI_CTL2 Register
        3. 7.6.3.3 CSI_STS Register
        4. 7.6.3.4 CSI_TX_ICR Register
        5. 7.6.3.5 CSI_TX_ISR Register
        6. 7.6.3.6 RESERVED Register
        7. 7.6.3.7 RESERVED Register
        8. 7.6.3.8 RESERVED Register
      4. 7.6.4  RESERVED Registers
      5. 7.6.5  AEQ Registers (Shared)
        1. 7.6.5.1 RESERVED Register
        2. 7.6.5.2 SFILTER_CFG Register
        3. 7.6.5.3 AEQ_CTL Register
        4. 7.6.5.4 AEQ_ERR_THOLD Register
        5. 7.6.5.5 RESERVED Register
        6. 7.6.5.6 RESERVED Register
      6. 7.6.6  Digital RX Port Registers
        1. 7.6.6.1  BCC_ERR_CTL Register
        2. 7.6.6.2  BCC_STATUS Register
        3. 7.6.6.3  RESERVED Register
        4. 7.6.6.4  RESERVED Register
        5. 7.6.6.5  FPD3_CAP Register
        6. 7.6.6.6  RAW_EMBED_DTYPE Register
        7. 7.6.6.7  FPD3_PORT_SEL Register
        8. 7.6.6.8  RX_PORT_STS1 Register
        9. 7.6.6.9  RX_PORT_STS2 Register
        10. 7.6.6.10 RX_FREQ_HIGH Register
        11. 7.6.6.11 RX_FREQ_LOW Register
        12. 7.6.6.12 SENSOR_STS_0 Register
        13. 7.6.6.13 SENSOR_STS_1 Register
        14. 7.6.6.14 SENSOR_STS_2 Register
        15. 7.6.6.15 SENSOR_STS_3 Register
        16. 7.6.6.16 RX_PAR_ERR_HI Register
        17. 7.6.6.17 RX_PAR_ERR_LO Register
        18. 7.6.6.18 BIST_ERR_COUNT Register
        19. 7.6.6.19 BCC_CONFIG Register
        20. 7.6.6.20 DATAPATH_CTL1 Register
        21. 7.6.6.21 DATAPATH_CTL2 Register
        22. 7.6.6.22 SER_ID Register
        23. 7.6.6.23 SER_ALIAS_ID Register
        24. 7.6.6.24 SlaveID[0] Register
        25. 7.6.6.25 SlaveID[1] Register
        26. 7.6.6.26 SlaveID[2] Register
        27. 7.6.6.27 SlaveID[3] Register
        28. 7.6.6.28 SlaveID[4] Register
        29. 7.6.6.29 SlaveID[5] Register
        30. 7.6.6.30 SlaveID[6] Register
        31. 7.6.6.31 SlaveID[7] Register
        32. 7.6.6.32 SlaveAlias[0] Register
        33. 7.6.6.33 SlaveAlias[1] Register
        34. 7.6.6.34 SlaveAlias[2] Register
        35. 7.6.6.35 SlaveAlias[3] Register
        36. 7.6.6.36 SlaveAlias[4] Register
        37. 7.6.6.37 SlaveAlias[5] Register
        38. 7.6.6.38 SlaveAlias[6] Register
        39. 7.6.6.39 SlaveAlias[7] Register
        40. 7.6.6.40 PORT_CONFIG Register
        41. 7.6.6.41 BC_GPIO_CTL0 Register
        42. 7.6.6.42 BC_GPIO_CTL1 Register
        43. 7.6.6.43 RAW10_ID Register
        44. 7.6.6.44 RAW12_ID Register
        45. 7.6.6.45 CSI_VC_MAP Register
        46. 7.6.6.46 LINE_COUNT_1 Register
        47. 7.6.6.47 LINE_COUNT_0 Register
        48. 7.6.6.48 LINE_LEN_1 Register
        49. 7.6.6.49 LINE_LEN_0 Register
        50. 7.6.6.50 FREQ_DET_CTL Register
        51. 7.6.6.51 MAILBOX_0 Register
        52. 7.6.6.52 MAILBOX_1 Register
        53. 7.6.6.53 CSI_RX_STS Register
        54. 7.6.6.54 CSI_ERR_COUNTER Register
        55. 7.6.6.55 PORT_CONFIG2 Register
        56. 7.6.6.56 PORT_PASS_CTL Register
        57. 7.6.6.57 SEN_INT_RISE_CTL Register
        58. 7.6.6.58 SEN_INT_FALL_CTL Register
      7. 7.6.7  RESERVED Registers
      8. 7.6.8  Digital CSI-2 Debug Registers (Shared)
        1. 7.6.8.1  CSI_FRAME_COUNT_HI Register
        2. 7.6.8.2  CSI_FRAME_COUNT_LO Register
        3. 7.6.8.3  CSI_FRAME_ERR_COUNT_HI Register
        4. 7.6.8.4  CSI_FRAME_ERR_COUNT_LO Register
        5. 7.6.8.5  CSI_LINE_COUNT_HI Register
        6. 7.6.8.6  CSI_LINE_COUNT_LO Register
        7. 7.6.8.7  CSI_LINE_ERR_COUNT_HI Register
        8. 7.6.8.8  CSI_LINE_ERR_COUNT_LO Register
        9. 7.6.8.9  RESERVED Register
        10. 7.6.8.10 RESERVED Register
        11. 7.6.8.11 RESERVED Register
        12. 7.6.8.12 RESERVED Register
        13. 7.6.8.13 RESERVED Register
        14. 7.6.8.14 RESERVED Register
        15. 7.6.8.15 RESERVED Register
        16. 7.6.8.16 RESERVED Register
      9. 7.6.9  RESERVED (Shared)
        1. 7.6.9.1 RESERVED Registers
        2. 7.6.9.2 REFCLK_FREQ Register
        3. 7.6.9.3 RESERVED Registers
      10. 7.6.10 Indirect Access Registers (Shared)
        1. 7.6.10.1 IND_ACC_CTL Register
        2. 7.6.10.2 IND_ACC_ADDR Register
        3. 7.6.10.3 IND_ACC_DATA Register
      11. 7.6.11 Digital Registers (Shared)
        1. 7.6.11.1  BIST Control Register
        2. 7.6.11.2  RESERVED Register
        3. 7.6.11.3  RESERVED Register
        4. 7.6.11.4  RESERVED Register
        5. 7.6.11.5  RESERVED Register
        6. 7.6.11.6  MODE_IDX_STS Register
        7. 7.6.11.7  LINK_ERROR_COUNT Register
        8. 7.6.11.8  FPD3_ENC_CTL Register
        9. 7.6.11.9  RESERVED Register
        10. 7.6.11.10 FV_MIN_TIME Register
        11. 7.6.11.11 RESERVED Register
        12. 7.6.11.12 GPIO_PD_CTL Register
        13. 7.6.11.13 RESERVED Register
      12. 7.6.12 RESERVED Registers
      13. 7.6.13 Digital RX Port Debug Registers (Paged)
        1. 7.6.13.1  PORT_DEBUG Register
        2. 7.6.13.2  RESERVED Register
        3. 7.6.13.3  AEQ_CTL2 Register
        4. 7.6.13.4  AEQ_STATUS Register
        5. 7.6.13.5  ADAPTIVE_EQ_BYPASS Register
        6. 7.6.13.6  AEQ_MIN_MAX Register
        7. 7.6.13.7  SFILTER_STS_0 Register
        8. 7.6.13.8  SFILTER_STS_1 Register
        9. 7.6.13.9  PORT_ICR_HI Register
        10. 7.6.13.10 PORT_ICR_LO Register
        11. 7.6.13.11 PORT_ISR_HI Register
        12. 7.6.13.12 PORT_ISR_LO Register
        13. 7.6.13.13 FC_GPIO_STS Register
        14. 7.6.13.14 FC_GPIO_ICR Register
        15. 7.6.13.15 SEN_INT_RISE_STS Register
        16. 7.6.13.16 SEN_INT_FALL_STS Register
      14. 7.6.14 RESERVED Registers
      15. 7.6.15 FPD3 RX ID Registers (Shared)
        1. 7.6.15.1 FPD3_RX_ID0 Register
        2. 7.6.15.2 FPD3_RX_ID1 Register
        3. 7.6.15.3 FPD3_RX_ID2 Register
        4. 7.6.15.4 FPD3_RX_ID3 Register
        5. 7.6.15.5 FPD3_RX_ID4 Register
        6. 7.6.15.6 FPD3_RX_ID5 Register
      16. 7.6.16 RESERVED Registers
      17. 7.6.17 RX Port I2C Addressing Registers (Shared)
        1. 7.6.17.1 I2C_RX0_ID Register
        2. 7.6.17.2 I2C_RX1_ID Register
        3. 7.6.17.3 I2C_RX2_ID Register
        4. 7.6.17.4 I2C_RX3_ID Register
      18. 7.6.18 RESERVED Registers
      19. 7.6.19 Indirect Access Registers
      20.      317
      21. 7.6.20 Digital Page 0 Indirect Registers
        1. 7.6.20.1  RESERVED
        2. 7.6.20.2  PGEN_CTL
        3. 7.6.20.3  PGEN_CFG
        4. 7.6.20.4  PGEN_CSI_DI
        5. 7.6.20.5  PGEN_LINE_SIZE1
        6. 7.6.20.6  PGEN_LINE_SIZE0
        7. 7.6.20.7  PGEN_BAR_SIZE1
        8. 7.6.20.8  PGEN_BAR_SIZE0
        9. 7.6.20.9  PGEN_ACT_LPF1
        10. 7.6.20.10 PGEN_ACT_LPF0
        11. 7.6.20.11 PGEN_TOT_LPF1
        12. 7.6.20.12 PGEN_TOT_LPF0
        13. 7.6.20.13 PGEN_LINE_PD1
        14. 7.6.20.14 PGEN_LINE_PD0
        15. 7.6.20.15 PGEN_VBP
        16. 7.6.20.16 PGEN_VFP
        17. 7.6.20.17 PGEN_COLOR0
        18. 7.6.20.18 PGEN_COLOR1
        19. 7.6.20.19 PGEN_COLOR2
        20. 7.6.20.20 PGEN_COLOR3
        21. 7.6.20.21 PGEN_COLOR4
        22. 7.6.20.22 PGEN_COLOR5
        23. 7.6.20.23 PGEN_COLOR6
        24. 7.6.20.24 PGEN_COLOR7
        25. 7.6.20.25 PGEN_COLOR8
        26. 7.6.20.26 PGEN_COLOR9
        27. 7.6.20.27 PGEN_COLOR10
        28. 7.6.20.28 PGEN_COLOR11
        29. 7.6.20.29 PGEN_COLOR12
        30. 7.6.20.30 PGEN_COLOR13
        31. 7.6.20.31 PGEN_COLOR14
        32. 7.6.20.32 PGEN_COLOR15
        33. 7.6.20.33 CSI_TCK_PREP
        34. 7.6.20.34 CSI_TCK_ZERO
        35. 7.6.20.35 CSI_TCK_TRAIL
        36. 7.6.20.36 CSI_TCK_POST
        37. 7.6.20.37 CSI_THS_PREP
        38. 7.6.20.38 CSI_THS_ZERO
        39. 7.6.20.39 CSI_THS_TRAIL
        40. 7.6.20.40 CSI_THS_EXIT
        41. 7.6.20.41 CSI1_TPLX
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  10. 9 Power Supply Recommendations
    1. 9.1 VDD Power Supply
    2. 9.2 Power-Up Sequencing
      1. 9.2.1 PDB Pin
      2. 9.2.2 System Initialization
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground
      2. 10.1.2 Routing FPD-Link III Signal Traces and PoC Filter
      3. 10.1.3 CSI-2 Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.24.2 Internally Generated FrameSync

In Internal FrameSync mode, an internally generated FrameSync signal is sent to one or more of the attached FPD3 Serializers through a GPIO signal in the back channel.

FrameSync operation is controlled by the FS_CTL, FS_HIGH_TIME_x, and FS_LOW_TIME_x 0x18 – 0x1C registers (Table 7-42 through Table 7-46). The resolution of the FrameSync generator clock (FS_CLK_PD) is derived from the back channel frame period (BC_FREQ_SELECT register). For 50-Mbps back-channel operation, the frame period is 600 ns (30 bits × 20 ns/bit). For each 2.5-Mbps back channel operation, the frame period is 12 µs (30 bits × 400 ns/bit).

Once enabled, the FrameSync signal is sent continuously based on the programmed conditions.

Enabling the internal FrameSync mode is done by setting the FS_GEN_ENABLE control in the FS_CTL register to a value of 1. The FS_MODE field controls the clock source used for the FrameSync generation. The FS_GEN_MODE field configures whether the duty cycle of the FrameSync is 50/50 or whether the high and low periods are controlled separately. The FrameSync high and low periods are controlled by the FS_HIGH_TIME and FS_LOW_TIME registers.

The accuracy of the internally generated FrameSync is directly dependent on the accuracy of the 25-MHz oscillator used as the reference clock.

GUID-22770563-8785-4F89-8D79-4C25D33F921B-low.gifFigure 7-14 Internal FrameSync
GUID-58E823FD-5B2F-4203-9B29-54C1F15C7B3A-low.gifFigure 7-15 Internal FrameSync Signal

The following example shows generation of a FrameSync signal at 60 pulses per second. Mode settings:

  • Programmable High/Low periods: FS_GEN_MODE 0x18[1]=0
  • Use port 0 back channel frame period: FS_MODE 0x18[7:4]=0x0
  • Back channel rate of 50 Mbps: BC_FREQ_SELECT for port 0 0x58[2:0]=110b
  • Initial FS state of 0: FS_INIT_STATE 0x18[2]=0

Based on mode settings, the FrameSync is generated based upon FS_CLK_PD of 12 us.

The total period of the FrameSync is (1 sec / 60 hz) / 600 ns or approximately 27,778 counts.

For a 10% duty cycle, set the high time to 2,776 (0x0AD7) cycles, and the low time to 24,992 (0x61A0) cycles:

  • FS_HIGH_TIME_1: 0x19=0x0A
  • FS_HIGH_TIME_0: 0x1A=0xD7
  • FS_LOW_TIME_1: 0x1B=0x61
  • FS_LOW_TIME_0: 0x1C=0xA0