JAJSKM4 データシート

JAJSKM4A november 2020 – november 2020 DS90UB662-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTD|64
- MPQF141C

サーマルパッド・メカニカル・データ

発注情報

jajskm4a_oa

7.5.1 Serial Control Bus

The DS90UB662-Q1 implements two I2C-compatible serial control buses. Both I2C ports support local device configuration and incorporate a bidirectional control channel (BCC) that allows communication with a remote serializers as well as remote I2C slave devices.

The device address is set through a resistor divider connected to the IDx pin (R1 and R2 – see Figure 7-19).

Figure 7-19 Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most applications, TI recommends a 4.7-kΩ pullup resistor to VDDIO. However, the pullup resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

The IDX pin configures the control interface to one of eight possible device addresses. A pullup resistor and a pulldown resistor may be used to set the appropriate voltage ratio between the IDX input pin (V_IDX) and V_(VDD18), each ratio corresponding to a specific device address. See Table 7-15, Serial Control Bus Addresses for IDX.

Table 7-15 Serial Control Bus Addresses for IDX

NO.	V_IDX VOLTAGE RANGE			V_IDX TARGET VOLTAGE	SUGGESTED STRAP RESISTORS (1% TOL)		PRIMARY ASSIGNED I2C ADDRESS
NO.	V_MIN	V_TYP	V_MAX	VDD18 = 1.80 V	R_HIGH ( kΩ )	R_LOW ( kΩ )	7-BIT	8-BIT
0	0	0	0.131 × V_(VDD18)	0	OPEN	10.0	0x30	0x60
1	0.179 × V_(VDD18)	0.213 × V_(VDD18)	0.247 × V_(VDD18)	0.374	88.7	23.2	0x32	0x64
2	0.296 × V_(VDD18)	0.330 × V_(VDD18)	0.362 × V_(VDD18)	0.582	75.0	35.7	0x34	0x68
3	0.412 × V_(VDD18)	0.443 × V_(VDD18)	0.474 × V_(VDD18)	0.792	71.5	56.2	0x36	0x6C
4	0.525 × V_(VDD18)	0.559 × V_(VDD18)	0.592 × V_(VDD18)	0.995	78.7	97.6	0x38	0x70
5	0.642 × V_(VDD18)	0.673 × V_(VDD18)	0.704 × V_(VDD18)	1.202	39.2	78.7	0x3A	0x74
6	0.761 × V_(VDD18)	0.792 × V_(VDD18)	0.823 × V_(VDD18)	1.420	25.5	95.3	0x3C	0x78
7	0.876 × V_(VDD18)	V_(VDD18)	V_(VDD18)	1.8	10.0	OPEN	0x3D	0x7A

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 7-20.

Figure 7-20 START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it acknowledges (ACKs) the master by driving the SDA bus low. If the address does not match one of the slave addresses of the device, it not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs can also occur on the bus when data transmissions are in process. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 7-21 and a WRITE is shown in Figure 7-22.

Figure 7-21 Serial Control Bus — READ

Figure 7-22 Serial Control Bus — WRITE

Figure 7-23 Basic Operation

The I2C Master located at the Deserializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to I2C Communication Over FPD-Link III With Bidirectional Control Channel (SNLA131) and I2C over DS90UB913/4 FPD-Link III With Bidirectional Control Channel (SNLA222).