JAJSGI8D
April 2016 – October 2019
DS90UB914A-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions: DS90UB914A-Q1 Deserializer
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
AC Timing Specifications (SCL, SDA) - I2C-Compatible
8.7
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
8.8
Deserializer Switching Characteristics
8.9
Typical Characteristics
9
Parameter Measurement Information
9.1
Timing Diagrams and Test Circuits
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Serial Frame Format
10.3.2
Line Rate Calculations for the DS90UB913A/914A
10.3.3
Deserializer Multiplexer Input
10.3.4
Error Detection
10.3.5
Synchronizing Multiple Cameras
10.3.6
General-Purpose I/O (GPIO) Descriptions
10.3.7
LVCMOS VDDIO Option
10.3.8
EMI Reduction
10.3.8.1
Deserializer Staggered Output
10.3.8.2
Spread Spectrum Clock Generation (SSCG) on the Deserializer
10.3.9
Pixel Clock Edge Select (TRFB / RRFB)
10.3.10
Power Down
10.4
Device Functional Modes
10.4.1
DS90UB913A/914A Operation With External Oscillator as Reference Clock
10.4.2
DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
10.4.3
MODE Pin on Deserializer
10.4.4
Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
10.4.5
Built-In Self Test
10.4.6
BIST Configuration and Status
10.4.7
Sample BIST Sequence
10.5
Programming
10.5.1
Programmable Controller
10.5.2
Description of Bidirectional Control Bus and I2C Modes
10.5.3
I2C Pass-Through
10.5.4
Slave Clock Stretching
10.5.5
ID[x] Address Decoder on the Deserializer
10.5.6
Multiple Device Addressing
10.6
Register Maps
11
Application and Implementation
11.1
Application Information
11.1.1
Power Over Coax
11.1.2
Power-Up Requirements and PDB Pin
11.1.3
AC Coupling
11.1.4
Transmission Media
11.1.5
Adaptive Equalizer – Loss Compensation
11.2
Typical Applications
11.2.1
Coax Application
11.2.1.1
Design Requirements
11.2.1.2
Detailed Design Procedure
11.2.1.3
Application Curves
11.2.2
STP Application
11.2.2.1
Design Requirements
11.2.2.2
Detailed Design Procedure
11.2.2.3
Application Curves
12
Power Supply Recommendations
13
Layout
13.1
Layout Guidelines
13.1.1
Interconnect Guidelines
13.2
Layout Example
14
デバイスおよびドキュメントのサポート
14.1
ドキュメントのサポート
14.1.1
関連資料
14.2
ドキュメントの更新通知を受け取る方法
14.3
コミュニティ・リソース
14.4
商標
14.5
静電気放電に関する注意事項
14.6
Glossary
15
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHS|48
MPQF159B
サーマルパッド・メカニカル・データ
RHS|48
QFND509A
発注情報
jajsgi8d_oa
jajsgi8d_pm
11.2
Typical Applications