SNLS420D July   2012  – July 2015 DS90UB913Q-Q1 , DS90UB914Q-Q1

PRODUCTION DATA.  

1. 1 Features
2. 2 Applications
3. 3 Description
4. 4 Revision History
5. 5 Description continued
6. 6 Device Comparison Table
7. 7 Pin Configuration and Functions
8. 8 Specifications
   1. 8.1  Absolute Maximum Ratings
   2. 8.2  ESD Ratings
   3. 8.3  Recommended Operating Conditions
   4. 8.4  Thermal Information
   5. 8.5  Electrical Characteristics
   6. 8.6  Timing Requirements: Recommended for Serializer PCLK
   7. 8.7  AC Timing Specifications (SCL, SDA) - I2C Compliant
   8. 8.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant
   9. 8.9  Switching Characteristics: Serializer
   10. 8.10 Switching Characteristics: Deserializer
   11. 8.11 Typical Characteristics
9. 9 Parameter Measurement Information
   1. 9.1 AC Timing Diagrams and Test Circuits
10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
       1. 10.3.1  Serial Frame Format
       2. 10.3.2  Line Rate Calculations for the DS90UB91xQ
       3. 10.3.3  Deserializer Multiplexer Input
       4. 10.3.4  Error Detection
       5. 10.3.5  Description of Bidirectional Control Bus and I2C Modes
       6. 10.3.6  Slave Clock Stretching
       7. 10.3.7  I2C Pass-Through
       8. 10.3.8  ID[x] Address Decoder on the Serializer
       9. 10.3.9  ID[x] Address Decoder on the Deserializer
       10. 10.3.10 Programmable Controller
       11. 10.3.11 Synchronizing Multiple Cameras
       12. 10.3.12 General-Purpose I/O (GPIO) Descriptions
       13. 10.3.13 LVCMOS VDDIO Option
       14. 10.3.14 Deserializer - Adaptive Input Equalization (AEQ)
       15. 10.3.15 EMI Reduction
           1. 10.3.15.1 Deserializer Staggered Output
           2. 10.3.15.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
    4. 10.4 Device Functional Modes
       1. 10.4.1  DS90UB91xQ-Q1 Operation With External Oscillator as Reference Clock
       2. 10.4.2  DS90UB91xQ-Q1 Operation With Pixel Clock from Imager as Reference Clock
       3. 10.4.3  MODE Pin on Serializer
       4. 10.4.4  MODE Pin on Deserializer
       5. 10.4.5  Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
       6. 10.4.6  Multiple Device Addressing
       7. 10.4.7  Powerdown
       8. 10.4.8  Pixel Clock Edge Select (TRFB / RRFB)
       9. 10.4.9  Power-Up Requirements and PDB Pin
       10. 10.4.10 Built-In Self Test
       11. 10.4.11 BIST Configuration and Status
           1. 10.4.11.1 Sample BIST Sequence
    5. 10.5 Register Maps
11. 11Application and Implementation
    1. 11.1 Applications Information
    2. 11.2 Typical Application
       1. 11.2.1 Design Requirements
          1. 11.2.1.1 Transmission Media
          2. 11.2.1.2 Adaptive Equalizer - Loss Compensation
       2. 11.2.2 Detailed Design Procedure
       3. 11.2.3 Application Curve
12. 12Power Supply Recommendations
13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
14. 14Device and Documentation Support
    1. 14.1 Documentation Support
       1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Community Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
15. 15Mechanical, Packaging, and Orderable Information