SNLS488 March   2016 DS90UB921-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  PCLK Timing Requirements
    9. 6.9  Recommended Timing for the Serial Control Bus
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signal Filter
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 Input SSC Tolerance (SSCT)
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Remote Auto Power-Down Mode
      9. 7.3.9  Input PCLK Loss Detect
      10. 7.3.10 Serial Link Fault Detect
      11. 7.3.11 Pixel Clock Edge Select (TRFB)
      12. 7.3.12 Frequency Mode Optimizations
      13. 7.3.13 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
      14. 7.3.14 Internal Pattern Generation
      15. 7.3.15 GPIO[3:0] and GPO_REG[7:4]
        1. 7.3.15.1 GPIO[3:0] Enable Sequence
        2. 7.3.15.2 GPO_REG[7:4] Enable Sequence
      16. 7.3.16 I2S Transmitting
      17. 7.3.17 Built In Self Test (BIST)
        1. 7.3.17.1 BIST Configuration and Status
          1. 7.3.17.1.1 Sample BIST Sequence
        2. 7.3.17.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 AVMUTE Operation
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Supply voltage – VDD33 –0.3 4 V
Supply voltage – VDDIO –0.3 4 V
LVCMOS I/O voltage –0.3 VDDIO + 0.3 V
Serializer output voltage - DOUT± –0.3 2.75 V
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings - JEDEC

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±8000 V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings—IEC and ISO

VALUE UNIT
V(ESD) Electrostatic discharge RD = 330 Ω, CS = 150 pF IEC, powered-up only contact discharge (DOUT+, DOUT-) ±8000 V
IEC, powered-up only air-gap discharge (DOUT+, DOUT-) ±18000
RD = 330 Ω, CS = 150 and 330 pF ISO10605 contact discharge (DOUT+, DOUT-) ±8000 V
ISO10605 air-gap discharge (DOUT+, DOUT-) ±18000
RD = 2 kΩ, CS = 150 and 330 pF ISO10605 contact discharge (DOUT+, DOUT-) ±8000 V
ISO10605 air-gap discharge (DOUT+, DOUT-) ±18000

6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage (VDD33) 3 3.3 3.6 V
LVCMOS supply voltage (VDDIO) 3 3.3 3.6 V
1.71 1.8 1.89 V
Operating free-air temperature (TA) −40 25 105 °C
PCLK frequency, Coax operation, high frequency mode(1) 48 96 MHz
PCLK frequency, Coax operation, intermediate frequency mode(1) 24 48 MHz
PCLK frequency, Coax operation, low frequency mode(1) 15 24 MHz
PCLK frequency, STP operation, high frequency mode(1) 15 96 MHz
PCLK frequency, STP operation, low frequency mode(1) 5 15 MHz
Supply noise -- (DC-50MHz) 100 mVP-P
(1) For configuration of cable type and frequency mode, refer to Frequency Mode Optimizations.

6.5 Thermal Information

THERMAL METRIC(1) DS90UB921-Q1 UNIT
RHS (WQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 29 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.7
RθJB Junction-to-board thermal resistance 5.0
ψJT Junction-to-top characterization parameter 0.1
ψJB Junction-to-board characterization parameter 6.0
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
LVCMOS I/O DC SPECIFICATIONS
VIH High-level input voltage VDDIO = 3 V to 3.6 V PDB 2 VDDIO V
VIL Low-level input voltage VDDIO = 3 V to 3.6 V GND 0.8 V
IIN Input current VIN = 0 V or
VIN = VDDIO (3 V to 3.6 V) 		–10 ±1 10 µA
VIH High-level input voltage VDDIO = 3 V to 3.6 V DIN[23:0], HS, VS, DE, PCLK, I2S_CLK, I2S_WC, I2S_DA 2 VDDIO V
VDDIO = 1.71 V to 1.89 V 0.65 × VDDIO VDDIO V
VIL Low-level input voltage VDDIO = 3 V to 3.6 V GND 0.8 V
VDDIO = 1.71 V to 1.89 V GND 0.35 × VDDIO V
IIN Input current VIN = 0 V or
VIN = VDDIO		 VDDIO = 3 V to 3.6 V –10 ±1 10 µA
VDDIO = 1.71 V to 1.89 V –10 ±1 10 µA
VOH High-level output voltage IOH = –4 mA VDDIO = 3 V to 3.6 V GPIO[3:0], GPO_REG[7:4], REM_INTB 2.4 VDDIO V
VDDIO = 1.71 V to 1.89 V VDDIO – 0.45 VDDIO V
VOL Low-level output voltage IOH = 4 mA VDDIO = 3 V to 3.6 V GND 0.4 V
VDDIO = 1.71 V to 1.89 V GND 0.35 V
IOS Output short-circuit current VOUT = 0 V –50 mA
IOZ TRI-STATE output current VOUT = 0 V or
VOUT = VDDIO
PDB = L		 –10 10 µA
FPD-LINK III CML DRIVER DC SPECIFICATIONS
VOD Differential output voltage (DOUT+) – (DOUT–) RL = 100 Ω, see Figure 1 DOUT± 700 800 1000 mVp-p
VOUT Single-ended output voltage (DOUT+ or DOUT-) RL = 50 Ω
See Figure 2		 350 400 500 mV
ΔVOD Output voltage unbalance 1 50 mV
VOS Offset voltage — single-ended RL = 100 Ω
See Figure 1		 2.5 – 0.5 × VOD V
ΔVOS Offset voltage unbalanced single-ended 1 50 mV
IOS Output short-circuit current DOUT± = 0 V, PDB = L or H –38 mA
RT Internal termination resistor — single-ended 40 50 62 Ω
SERIAL CONTROL BUS
VIH Input high level, I2C SDA, SCL 0.7 × VDD33 VDD33 V
VIL Input low-level voltage, I2C 0.3 × VDD33 V
VHY Input hysteresis, I2C > 50 mV
VOL Output Low Level, I2C IOL = +1.25mA 0 0.36 V
IIN Input Current, I2C VIN = 0V or
VIN = VDD33		 –10 10 µA
CIN Input capacitance, I2C < 5 pF
SUPPLY CURRENT
IDD1 Supply Current
(includes load current)
RL = 100Ω, f = 96MHz		 Checker Board Pattern,
See Figure 3		 VDD33 = 3.6V 148 180 mA
IDDIO1 VDDIO = 3.6V 90 180 μA
VDDIO = 1.89V 1 3 mA
IDDS1 Supply Current Remote Auto Power Down Mode 0x01[7] = 1, deserializer is powered down VDD33 = 3.6V 1.2 3 mA
IDDIOS1 VDDIO = 3.6V 65 200 μA
VDDIO = 1.89V 55 200 μA
IDDS2 Supply Current Power Down PDB = L, All LVCMOS inputs are not connected (NC) or tied to GND VDD33 = 3.6V 1 3 mA
IDDIOS2 VDDIO = 3.6V 65 200 μA
VDDIO = 1.89V 55 200 μA
IDDS3 Supply Current Sleep State 0x01[7] = 1, PCLK is removed. VDD33 = 3.6V 55 mA
IDDIOS3 VDDIO = 3.6V 80 μA
VDDIO = 1.89V 1 mA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or Notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at nominal conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
PARAMETER TEST CONDITIONS PIN/FREQUENCY MIN TYP MAX UNIT
GPIO BIT RATE
BRF Forward channel bit rate See(4) ƒ = 5 – 96 MHz
GPIO[3:0]		 0.25 × ƒ Mbps
BRB Back channel bit rate STP cable - HFMODE GPIO[3:0] 60 kbps
STP cable - LFMODE
Coax cable - HFMODE, IFMODE, or LFMODE		 40 kbps
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or Notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at nominal conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.
(4) Specification is ensured by design and is not tested in production.

6.8 PCLK Timing Requirements

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN NOM MAX UNIT
tTCP PCLK period with STP cable, see(1)
ƒ = 5 to 96 MHz		 10.41 T 200 ns
PCLK period with Coax cable, see(1)
ƒ = 15 to 96 MHz		 10.41 T 66.7 ns
tCIH PCLK input high time; pin/frequency: PCLK 0.4*T 0.5*T 0.6*T ns
tCIL PCLK input low time; pin/frequency: PCLK 0.4*T 0.5*T 0.6*T ns
tCLKT PCLK input transition time(1), see Figure 4; ƒ = 5 MHz 4 ns
PCLK input transition time(1), see Figure 4; ƒ = 96 MHz 0.5 ns
tIJIT PCLK input jitter, bit error rate ≤ 10–10
ƒ / 40 < jitter freq < ƒ / 20
ƒ = 5 to 78 MHz
(1)(2)
Paired with DS90UB926Q-Q1		 0.35 UI
PCLK input jitter, bit error rate ≤ 10–10
ƒ / 40 < jitter freq < ƒ / 20
f = 5 - 85MHz
(1)(2)
Paired with DS90UB928Q-Q1		 0.35 UI
PCLK input jitter, bit error rate ≤ 10–10
ƒ / 40 < jitter freq < ƒ / 20
f = 25 - 96MHz
(1)(2)
Paired with DS90UB940-Q1, or DS90UB948-Q1		 0.35 UI
(1) Specification is ensured by characterization and is not tested in production.
(2) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 × PCLK). The UI scales with PCLK frequency.

6.9 Recommended Timing for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN TYP MAX UNIT
ƒSCL SCL clock frequency Standard mode 0 100 kHz
Fast mode 0 400 kHz
tLOW SCL low period Standard mode 4.7 µs
Fast mode 1.3 µs
tHIGH SCL high period Standard mode 4 µs
Fast mode 0.6 µs
tHD;STA Hold time for a start or a repeated start condition,
see Figure 10 		Standard mode 4 µs
Fast mode 0.6 µs
tSU:STA Set-up time for a start or a repeated start condition,
see Figure 10 		Standard mode 4.7 µs
Fast mode 0.6 µs
tHD;DAT Data hold time, see Figure 10 Standard mode 0 0.615 3.45 µs
Fast mode 0 0.615 0.9 µs
tSU;DAT Data set-up time, see Figure 10 Standard mode 250 0.56 ns
Fast mode 100 0.56 ns
tSU;STO Set-up time for STOP condition,
See Figure 10 		Standard mode 4 µs
Fast mode 0.6 µs
tBUF Bus free time
between STOP and START,
SeeFigure 10 		Standard mode 4.7 µs
Fast mode 1.3 µs
tr SCL and SDA rise time,
See Figure 10 		Standard mode 430 1000 ns
Fast mode 200 300 ns
tf SCL and SDA fall time,
See Figure 10 		Standard mode 20 300 ns
Fast mode 20 300 ns
tsp Input filter 50 ns
DS90UB921-Q1 921VOD_STP.gif Figure 1. Serializer Differential VOD DC Output
DS90UB921-Q1 921VOut_coax.gif Figure 2. Serializer Single-ended VOUT DC Output
DS90UB921-Q1 30143346.gif Figure 3. Checker Board Data Pattern
DS90UB921-Q1 30143330.gif Figure 4. Serializer Input Clock Transition Time
DS90UB921-Q1 30143347.gif Figure 5. Serializer CML Output Load and Transition Time
DS90UB921-Q1 30143361.gif Figure 6. Serializer Setup and Hold Times
DS90UB921-Q1 30143349.gif Figure 7. Serializer Lock Time
DS90UB921-Q1 921delay.gif Figure 8. Serializer Delay Time
DS90UB921-Q1 tbit.gif Figure 9. Serializer CML Output Jitter
DS90UB921-Q1 30143336.gif Figure 10. Serial Control Bus Timing Diagram

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
tLHT CML Output Low-to-High Transition Time See Figure 5 DOUT+, DOUT- 80 ps
tHLT CML Output High-to-Low Transition Time 80 ps
tDIS Data Input Setup to PCLK See Figure 6 R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK 2.0 ns
tDIH Data Input Hold from PCLK 2.0 ns
tPLD Serializer PLL Lock Time See Figure 7 (1) f = 5 - 96MHz 131*T ns
tSD Delay — Latency See Figure 8 f = 5 - 96MHz 145*T ns
tTJIT Output Total Intrinsic Jitter, Jitter frequency > f/10
Bit Error Rate ≥10-10 (2) (3) 		RL = 100Ω
f = 96MHz
See Figure 9		 DOUT+, DOUT- 0.25 0.30 UI
(1) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by characterization and is not tested in production.
(3) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.

6.11 Typical Charateristics

DS90UB921-Q1 921CMLOUT.gif
Note: On the rising edge of each clock period, the CML driver outputs a low Stop bit, high Start bit, and 33 DC-scrambled data bits.
Figure 11. Serializer CML Driver Output with 96 MHz TX Pixel Clock
DS90UB921-Q1 921PCLK_CMLOUT_96.gif
Figure 12. Serializer CMLOUT Driver Output and 96 MHz LVCMOS PCLK Input