The DS90UB925Q-Q1 serializer, in conjunction with the DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video-display systems with HD formats and automotive vision systems with megapixel resolutions. The DS90UB925Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB925Q-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 data bits are serialized along the video control signals.
Serial transmission is optimized by a user selectable de-emphasis. EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
Changes from C Revision (April 2013) to D Revision
Changes from B Revision (August 2012) to C Revision
Changes from A Revision (July 2012) to B Revision
Changes from * Revision (March 2012) to A Revision
PIN NAME | PIN # | I/O, TYPE | DESCRIPTION |
---|---|---|---|
LVCMOS PARALLEL INTERFACE | |||
DIN[23:0] / R[7:0], G[7:0], B[7:0] | 25, 26, 27, 28, 29, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 1, 2 | I, LVCMOS w/ pull down |
Parallel Interface Data Input Pins Leave open if unused DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as GPIO1 DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as GPIO3 DIN16 / B0 can optionally be used as GPIO4 and DIN17 / B1 can optionally be used as GPIO5 |
HS | 3 | I, LVCMOS w/ pull down |
Horizontal Sync Input Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Table 6. |
VS | 4 | I, LVCMOS w/ pull down |
Vertical Sync Input Pin Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs. |
DE | 5 | I, LVCMOS w/ pull down |
Data Enable Input Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Table 6. |
PCLK | 10 | I, LVCMOS w/ pull down |
Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6. |
I2S_CLK, I2S_WC, I2S_DA | 13, 12, 11 | I, LVCMOS w/ pull down |
Digital Audio Interface Data Input Pins Leave open if unused I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as GPO_REG6. |
OPTIONAL PARALLEL INTERFACE | |||
I2S_DB | 44 | I, LVCMOS w/ pull down |
Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by MODE_SEL pin or configuration register Leave open if unused I2S_DB can optionally be used as DIN17 or GPO_REG5. |
GPIO[3:0] | 36, 35, 26, 25 | I/O, LVCMOS w/ pull down |
General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or configuration register. See Table 6. Leave open if unused. Shared with DIN9, DIN8, DIN1 and DIN0 |
GPO_REG[8:4] | 13, 12, 11, 44, 43 | O, LVCMOS w/ pull down |
General Purpose Outputs and set by configuration register. See Table 6. Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or DIN17, DIN16. |
CONTROL | |||
PDB | 21 | I, LVCMOS w/ pull-down |
Power-down Mode Input Pin PDB = H, device is enabled (normal operation) Refer to Power Up Requirements and PDB Pin section. PDB = L, device is powered down. When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and IDD is minimized. Control Registers are RESET. |
MODE_SEL | 24 | I, Analog | Device Configuration Select. See Table 4. |
I2C | |||
IDx | 6 | I, Analog | I2C Serial Control Bus Device ID Address Select External pull-up to VDD33 is required under all conditions, DO NOT FLOAT. Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 19. |
SCL | 8 | I/O, LVCMOS Open Drain |
I2C Clock Input / Output Interface Must have an external pull-up to VDD33, DO NOT FLOAT. Recommended pull-up: 4.7kΩ. |
SDA | 9 | I/O, LVCMOS Open Drain |
I2C Data Input / Output Interface Must have an external pull-up to VDD33, DO NOT FLOAT. Recommended pull-up: 4.7kΩ. |
STATUS | |||
INTB | 31 | O, LVCMOS Open Drain |
Interrupt INTB = H, normal INTB = L, Interrupt request Recommended pull-up: 4.7kΩ to VDDIO |
FPD-LINK III SERIAL INTERFACE | |||
DOUT+ | 20 | O, LVDS | True Output The output must be AC-coupled with a 0.1µF capacitor. |
DOUT- | 19 | O, LVDS | Inverting Output The output must be AC-coupled with a 0.1µF capacitor. |
CMF | 23 | Analog | Common Mode Filter. Connect 0.1µF to GND |
POWER AND GROUND (1) | |||
VDD33 | 22 | Power | Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND |
VDDIO | 30 | Power | LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND |
GND | DAP | Ground | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. |
REGULATOR CAPACITOR | |||
CAPHS12, CAPP12 | 17, 14 | CAP | Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each CAP pin. |
CAPL12 | 7 | CAP | Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this CAP pin. |
OTHERS | |||
NC | 16 | NC | Do not connect. |
RES[1:0] | 18, 15 | GND | Reserved. Tie to Ground. |