7.3.1 High Speed Forward Channel Data Transfer

The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or YUV data, sync signals, I²C, and I2S audio transmitted from Serializer to Deserializer. Figure 11 illustrates the serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled.

Figure 11. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.

7.3.2 Low Speed Back Channel Data Transfer

The Low-Speed Backward Channel (LS_BC) of the DS90UB925Q-Q1 provides bidirectional communication between the display and host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock information. This architecture provides a backward path across the serial link together with a high speed forward channel. The back channel contains the I²C, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.

7.3.3 Backward Compatible Mode

The DS90UB925Q-Q1 is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link II deserializers at 5-65 MHz of PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating at the line rate of 140 Mbps to 1.82 Gbps. The backward configuration mode can be set via MODE_SEL pin (Table 4) or the configuration register (Table 6). Note: frequency range = 15 – 65MHz when LFMODE = 0 and frequency range = 5 – <15MHz when LFMODE = 1.

7.3.4 Common Mode Filter Pin (CMF)

The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.

7.3.5 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:

• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See Figure 12.

Figure 12. Video Control Signal Filter Waveform

7.3.6 EMI Reduction Features

7.3.7 LVCMOS V_DDIO Option

1.8 V or 3.3 V Inputs and Outputs are powered from a separate V_DDIO supply to offer compatibility with external system interface signals.

7.3.8 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the host or through the V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power disable the link when the display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO have reached final levels; no external components are required. In the case of driven by the V_DDIO = 3.0V to 3.6V or V_DD33 directly, a 10 kohm resistor to the V_DDIO = 3.0V to 3.6V or V_DD33 , and a >10uF capacitor to the ground are required (See Figure 23).

7.3.9 Remote Auto Power Down Mode

The Serializer features a remote auto power down mode. During the power down mode of the pairing deserializer, the Serializer enters the remote auto power down mode. In this mode, the power dissipation of the Serializer is reduced significantly. When the Deserializer is powered up, the Serializer enters the normal power on mode automatically. This feature is enabled through the register bit 0x01[7] Table 6.

7.3.10 Input PCLK Loss Detect

The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again, the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registers values are still RETAINED.

7.3.11 Serial Link Fault Detect

The serial link fault detection is able to detect any of following seven (7) conditions:

1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked correctly

If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C Table 6.

7.3.12 Pixel Clock Edge Select (RFB)

The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines the edge that the data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB is LOW (‘0’), data is latched on the Falling edge of the PCLK.

7.3.13 Low Frequency Optimization (LFMODE)

The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency of the serializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed, a PDB reset is required.

7.3.14 Interrupt Pin — Functional Description And Usage (INTB)

1. On DS90UB925, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UB926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UB925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read ISR register .
5. A read to ISR will clear the interrupt at the DS90UB925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the INTB_IN (pin 16) on the DS90UB926Q-Q1. The system is now ready to return to step (1) at next falling edge of INTB_IN.

7.3.15 Internal Pattern Generation

The DS90UB925Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application Note AN-2198 (SNLA132).

7.3.16 GPIO[3:0] and GPO_REG[8:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB925Q-Q1 can be used as the general purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) application.

7.3.17 I2S Transmitting

In normal 24-bit RGB operation mode, the DS90UB925Q-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must maintain one fourth of the PCLK rate.

7.3.18 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. Note: BIST is not available in backwards compatible mode.

7.3.18.1 BIST Configuration and Status

The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or configuration register (Table 6) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to 35 bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the deserializer is locked or unlocked, the lock status can be read in the register. See Table 6.

7.3.18.1.1 Sample BIST Sequence

See Figure 13 for the BIST mode flow diagram.

Step 1: For the DS90UB925Q-Q1 and DS90UB926Q-Q1 FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin of DS90UB926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTC pin.

Step 2: The DS90UB925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.

Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 14 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements ( Rx Equalization).

Figure 13. Bist Mode Flow Diagram

7.3.18.2 Forward Channel And Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The deserializer then outputs a SSO pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.

Figure 14. Bist Waveforms

7.4.1 Configuration Select (MODE_SEL)

Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (V_R4) and V_DD33 to select one of the other 10 possible selected modes. See Figure 15 and Table 4.

Figure 15. MODE_SEL Connection Diagram

7.4.2 Repeater Application

The DS90UB925Q-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links to multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all receivers in the system.

7.4.2.1 Repeater Configuration

In the repeater application, in this document, the DS90UB925Q-Q1 is referred to as the Transmitter or transmit port (TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). Figure 16 shows the maximum configuration supported for Repeater implementations using the DS90UB925Q-Q1 (TX) and DS90UB926Q-Q1 (RX). Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver.

Figure 16. Maximum Repeater Application

In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C communications upstream or downstream to any I2C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the Receiver and is received by the Transmitter.

Figure 17 provides more detailed block diagram of a 1:2 repeater configuration.

Figure 17. 1:2 Repeater Configuration

7.4.2.2 Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter Figure 18.

1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33 with 4.7 kΩ resistors.
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin – Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB925Q-Q1 INTB pin. The signal must be pulled up to V_DDIO.

Figure 18. Repeater Connection Diagram

Table 5. Serial Control Bus Addresses for IDx