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The DS90UB927Q-Q1 serializer, in conjunction with a DS90UB928Q-Q1 or DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video display systens with HD formats and automotive vision systems with megapixel resolutions. The DS90UB927Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This device translates a FPD-Link video interface into a single-pair high-speed serialized interface. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB927Q-Q1 serializer embeds the clock and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and DC-balancing.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DS90UB927Q-Q1 | WQFN (40) | 6.00 mm x 6.00 mm |
Changes from C Revision (October 2012) to D Revision
Changes from B Revision (June 2012) to C Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
FPD-LINK INPUT INTERFACE | |||
RxCLKIN- | 35 | I, LVDS | Inverting LVDS Clock Input The pair requires external 100-Ω differential termination for standard LVDS levels |
RxCLKIN+ | 36 | I, LVDS | True LVDS Clock Input The pair requires external 100-Ω differential termination for standard LVDS levels |
RxIN[3:0]- | 37, 33, 31, 29 |
I, LVDS | Inverting LVDS Data Inputs Each pair requires external 100-Ω differential termination for standard LVDS levels |
RxIN[3:0]+ | 38, 34, 32, 30 |
I, LVDS | True LVDS Data Inputs Each pair requires external 100-Ω differential termination for standard LVDS levels |
LVCMOS PARALLEL INTERFACE | |||
BKWD | 22 | I, LVCMOS with pulldown |
Backward Compatible Mode Select BKWD = 0, interfacing to DS90UH926/8Q-Q1 (Default) BKWD = 1, interfacing to DS90UR906/8Q-Q1, DS90UR916Q Requires a 10-kΩ pullup if set HIGH |
GPIO[1:0] | 40, 39 | I/O, LVCMOS with pulldown |
General Purpose I/O See Table 1 |
I2S_DA I2S_DB I2S_DC I2S_DD |
3 4 5 6 |
I, LVCMOS with pulldown |
Digital Audio Interface I2S Data Inputs Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3 |
I2S_WC I2S_CLK |
1 2 |
I, LVCMOS with pulldown |
Digital Audio Interface I2S Word Clock and I2S Bit Clock Inputs Shared with GPIO_REG7 and GPIO_REG8 (Table 3) |
LFMODE | 25 | I, LVCMOS with pulldown |
Low Frequency Mode Select LFMODE = 0, 15 MHz ≤ RxCLKIN ≤ 85 MHz (Default) LFMODE = 1, 5 MHz ≤ RxCLKIN < 15 MHz Requires a 10-kΩ pullup if set HIGH |
MAPSEL | 23 | I, LVCMOS with pulldown |
FPD-Link Input Map Select MAPSEL = 0, LSBs on RxIN3± (Default) MAPSEL = 1, MSBs on RxIN3± See Figure 19 and Figure 20 Requires a 10-kΩ pullup if set HIGH |
REPEAT | 21 | I, LVCMOS with pulldown |
Repeater Mode Select REPEAT = 0, Repeater Mode disabled (Default) REPEAT = 1, Repeater Mode enabled Requires a 10-kΩ pullup if set HIGH |
OPTIONAL PARALLEL INTERFACE | |||
GPIO[3:2] | 6, 5 | I/O, LVCMOS with pulldown |
General Purpose I/O Shared with I2S_DD and I2S_DC (See Table 1) |
GPIO_REG [8:5] |
2, 1, 3, 4 | I/O, LVCMOS with pulldown |
Register-Only General Purpose I/O Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB (See Table 2) |
CONTROL AND CONFIGURATION | |||
IDx | 11 | I, Analog | I2C Address Select External pullup to VDD33 is required under all conditions. DO NOT FLOAT. Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider. See Figure 25 and Table 4 |
PDB | 18 | I, LVCMOS with pulldown |
Power-down Mode Input Pin Must be driven or pulled up to VDD33. Refer to Power Supply Recommendations. PDB = H, device is enabled (normal operation) PDB = L, device is powered down. When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and IDD is minimized. Control Registers are RESET. |
SCL | 9 | I/O, LVCMOS Open Drain |
I2C Clock Input / Output Interface Must have an external pullup to VDD33. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
SDA | 10 | I/O, LVCMOS Open Drain |
I2C Data Input / Output Interface Must have an external pullup to VDD33. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
STATUS | |||
INTB | 27 | O, LVCMOS Open Drain |
Interrupt INTB = H, normal INTB = L, Interrupt request Recommended pullup: 4.7 kΩ to VDDIO. DO NOT FLOAT. |
FPD-LINK III SERIAL INTERFACE | |||
CMF | 20 | Analog | Common Mode Filter. Connect 0.1 µF to GND (required) |
DOUT- | 16 | I/O, LVDS | Inverting Output The output must be AC-coupled with a 0.1-µF capacitor. |
DOUT+ | 17 | I/O, LVDS | True Output The output must be AC-coupled with a 0.1-µF capacitor. |
POWER(1) AND GROUND | |||
GND | DAP | Ground | Large metal contact at the bottom center of the device package Connect to the ground plane (GND) with at least 9 vias. |
VDD33_A VDD33_B |
19 26 |
Power | Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7-µF capacitor to GND |
VDDIO | 7, 24 | Power | LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7-µF capacitor to GND |
REGULATOR CAPACITOR | |||
CAPL12 | 8 | CAP | Decoupling capacitor connection for on-chip regulator Requires two 4.7-µF decoupling capacitors to GND |
CAPP12 CAPHS12 CAPLVD12 |
12 14 28 |
CAP | Decoupling capacitor connection for on-chip regulator Each requires a 4.7-µF decoupling capacitor to GND. |
OTHER | |||
RES[1:0] | 15, 13 | GND | Reserved Connect to GND. |