JAJSF25C March 2018 – January 2023 DS90UB936-Q1
PRODUCTION DATA
A valid 23-MHz to 26-MHz reference clock is required on the REFCLK pin 5 for precise frequency operation. The REFCLK frequency defines all internal clock timers, including the back channel rate, I2C timers, CSI-2 datarate, FrameSync signal parameters, and other timing critical internal circuitry. REFCLK input must be continuous. If the REFCLK input does not detect a transition more than 20 µS, this may cause a disruption in the CSI-2 output. REFCLK should be applied to the DS90UB936-Q1 only when the supply rails are above minimum levels (see GUID-C21665F1-6728-482C-BFD5-5F6E27F2032D.html#GUID-C21665F1-6728-482C-BFD5-5F6E27F2032D). At start-up, the DS90UB936-Q1 defaults to an internal oscillator to generate an backup internal reference clock at nominal frequency of 25 MHz ±10%.
The REFCLK LVCMOS input oscillator specifications are listed in #GUID-2AEE12D3-ECAF-41A8-B7AD-95287127AA19/SNLS4791032.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| REFERENCE CLOCK | ||||||
| Frequency tolerance | –40°C ≤ TA ≤ 105°C | ±50 | ppm | |||
| Frequency stability | Aging | ±50 | ppm | |||
| Amplitude | 800 | 1200 | V(VDDIO) | mVp-p | ||
| Symmetry | Duty Cycle | 40% | 50% | 60% | ||
| Rise and fall time | 10% – 90% | 6 | ns | |||
| Jitter | 200 kHz – 10 MHz | 50 | 200 | ps p-p | ||
| Frequency | 23 | 25 | 26 | MHz | ||
| Spread-spectrum clock modulation percentage | Center Spread | -0.5 | +0.5 | % | ||
| Down Spread | -1 | 0 | % | |||
| Spread-spectrum clock modulation frequency | 33 | KHz | ||||