JAJSF25 データシート

JAJSF25C March 2018 – January 2023 DS90UB936-Q1

PRODUCTION DATA

9.2 Power-Up Sequencing

The power-up sequence for the DS90UB936-Q1 is as follows:

Figure 9-1 Power Supply Sequencing VDD_SEL = LOW, Internal VDD 1.1-V Supply

Figure 9-2 Power Supply Sequencing VDD_SEL = HIGH, External VDD 1.1-V Supply

Table 9-1 Timing Diagram for the Power Supply Start-Up Sequence

PARAMETER		MIN	TYP	UNIT	NOTES
T0	VDD18 rise time	0.05		ms	at 10/90%
T1	VDDIO rise time	0.2	1	ms	at 10/90%
T2	VDD18 High to VDD11 applied	0		ms	N/A when VDD_SEL = LOW
T3	VDD11 rise time	0.2	1	ms	at 10/90%
T4	VDD to PDB	0		ms	After all VDD are stable
T5	PDB high time before PDB hard reset	1		ms
T6	PDB high to low pulse width	2		ms	Hard reset (optional)
T7	PDB to I2C ready (IDX and MODE valid) delay	2		ms

Note: VDDIO can come up either before or after VDD18.