JAJSF25C March 2018 – January 2023 DS90UB936-Q1
PRODUCTION DATA
Two register bits allow controlling the CSI-2 Transmitter output state. If the OUTPUT_SLEEP_STATE_SELECT (OSS_SEL) control is set to 0 in the GENERAL_CFG 0x02 register (see Table 7-21), the CSI-2 Transmitter outputs are forced to the HS-0 state. If the OUTPUT_ENABLE (OEN) register bit is set to 0 in the GENERAL_CFG register, the CSI-2 pins are set to the high-impedance state.
For normal operation (OSS_SEL and OEN both set to 1), activity on either of the Rx Port determines the state of the CSI-2 outputs. The CSI-2 Pin State during FPD-Link III inactive includes two options, controlled by the OUTPUT_EN_MODE bit in the GENERAL_CFG register and FWD_PORTx_DIS in the FWD_CTL1 register 0x20. If OUTPUT_EN_MODE is set to 0, a lack of activity will force the outputs to Hi-Z condition. If OUTPUT_EN_MODE is set to 1, or if the forwarding for the Rx Port is disabled (FWD_PORTx_DIS = 1), the output enters LP-11 state as there is no data available to the CSI-2 Transmitter input. The FPD-Link III inputs are considered active if the Receiver indicates valid lock to the incoming signal. For a CSI-2 TX port, lock is considered valid if any Received port mapped to the TX port is indicating Lock. See section GUID-5AF6E34F-6C1D-4A10-BAFB-50D60A86E3DD.html#GUID-5AF6E34F-6C1D-4A10-BAFB-50D60A86E3DD for description of Rx port forwarding.
| PDB pin | OSS_SEL | OEN | OUTPUT_OEN_MODE | FWD_PORTx_DIS | FPD-Link III INPUT | CSI-2 PIN STATE |
|---|---|---|---|---|---|---|
| 0 | X | X | X | X | X | Hi-Z |
| 1 | 0 | X | X | X | X | HS-0 |
| 1 | 1 | 0 | X | X | X | Hi-Z |
| 1 | 1 | 1 | 0 | X | All inactive | Hi-Z |
| 1 | 1 | 1 | 1 | X | All inactive | LP-11 |
| 1 | 1 | 1 | X | 1 | Any active | LP-11 |
| 1 | 1 | 1 | X | 0 | Any active | Valid |