8.6.1.39 SCL_High_Time Register (Address = 26h) [reset = 83h]
SCL_High_Time is described in Table 50.
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Table 50. SCL_High_Time Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-0 |
SCL_HIGH_TIME |
R/W |
83h |
I2C Master SCL High Time.
This field configures the high pulse width of the SCL output when the De-Serializer is the Master on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5-µs SCL high time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz. |