8.6.1.42 I2S_Control Register (Address = 2Bh) [reset = 0h]
I2S_Control is described in Table 53.
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Table 53. I2S_Control Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-4 |
RESERVED |
R/W |
0h |
Reserved |
3 |
I2S_FIFO
_OVERRUN_STATUS |
R |
0h |
I2S FIFO Overrun Status. |
2 |
I2S_FIFO
_UNDERRUN_STATUS |
R |
0h |
I2S FIFO Underrun Status. |
1 |
I2S_FIFO
_ERROR_RESET |
R/W |
0h |
I2S Fifo Error Reset.
1: Clears FIFO Error |
0 |
I2S_DATA
_FALLING_EDGE |
R/W |
0h |
I2S Clock Edge Select.
1: I2S Data is strobed on the Rising Clock Edge.
0: I2S Data is strobed on the Falling Clock Edge. |