JAJSH34
March 2019
DS90UB940N-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
代表的なアプリケーション
4
改訂履歴
5
概要（続き）
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
DC Electrical Characteristics
7.6
AC Electrical Characteristics
7.7
Timing Requirements for the Serial ControlBus
7.8
Switching Characteristics
7.9
Timing Diagrams and Test Circuits
7.10
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
High-Speed Forward Channel Data Transfer
8.3.2
Low-Speed Back Channel Data Transfer
8.3.3
FPD-Link III Port Register Access
8.3.4
Clock and Output Status
8.3.5
LVCMOS VDDIO Option
8.3.6
Power Down (PDB)
8.3.7
Interrupt Pin — Functional Description and Usage (INTB_IN)
8.3.8
General-Purpose I/O (GPIO)
8.3.8.1
GPIOx and D_GPIOx Pin Configuration
8.3.8.2
Back Channel Configuration
8.3.8.3
GPIO_REG[8:5] Configuration
8.3.9
SPI Communication
8.3.9.1
SPI Mode Configuration
8.3.9.2
Forward Channel SPI Operation
8.3.9.3
Reverse Channel SPI Operation
8.3.10
Backward Compatibility
8.3.11
Adaptive Equalizer
8.3.11.1
Transmission Distance
8.3.11.2
Adaptive Equalizer Algorithm
8.3.11.3
AEQ Settings
8.3.11.3.1
AEQ Start-Up and Initialization
8.3.11.3.2
AEQ Range
8.3.11.3.3
AEQ Timing
8.3.12
I2S Audio Interface
8.3.12.1
I2S Transport Modes
8.3.12.2
I2S Jitter Cleaning
8.3.12.3
MCLK
8.3.13
Built-In Self Test (BIST)
8.3.13.1
BIST Configuration and Status
8.3.13.1.1
Sample BIST Sequence
8.3.13.2
Forward Channel and Back Channel Error Checking
8.3.14
Internal Pattern Generation
8.4
Device Functional Modes
8.4.1
Configuration Select
8.4.1.1
1-Lane FPD-Link III Input, 4 MIPI® Lanes Output
8.4.1.2
1-Lane FPD-Link III Input, 2 MIPI® Lanes Output
8.4.1.3
2-Lane FPD-Link III Input, 4 MIPI® Lanes Output
8.4.1.4
2-Lane FPD-Link III Input, 2 MIPI® Lanes Output
8.4.1.5
1- or 2-Lane FPD-Link III Input, 2 or 4 MIPI® Lanes Output in Replicate
8.4.2
MODE_SEL[1:0]
8.4.3
CSI-2 Interface
8.4.4
Input Display Timing
8.4.5
MIPI® CSI-2 Output Data Formats
8.4.6
Non-Continuous / Continuous Clock
8.4.7
Ultra-Low-Power State (ULPS)
8.4.8
CSI-2 Data Identifier
8.5
Programming
8.5.1
Serial Control Bus
8.5.2
Multi-Master Arbitration Support
8.5.3
I2C Restrictions on Multi-Master Operation
8.5.4
Multi-Master Access to Device Registers for Newer FPD-Link III Devices
8.5.5
Multi-Master Access to Device Registers for Older FPD-Link III Devices
8.5.6
Restrictions on Control Channel Direction for Multi-Master Operation
8.6
Register Maps
8.6.1
DS90UB940N-Q1 Registers
8.6.1.1
I2C_Device_ID Register (Address = 0h) [reset = Strap]
Table 12.
I2C_Device_ID Register Field Descriptions
8.6.1.2
Reset Register (Address = 1h) [reset = 4h]
Table 13.
Reset Register Field Descriptions
8.6.1.3
General_Configuration_0 Register (Address = 2h) [reset = 80h]
Table 14.
General_Configuration_0 Register Field Descriptions
8.6.1.4
General_Configuration_1 Register (Address = 3h) [reset = F0h]
Table 15.
General_Configuration_1 Register Field Descriptions
8.6.1.5
BCC_Watchdog_Control Register (Address = 4h) [reset = FEh]
Table 16.
BCC_Watchdog_Control Register Field Descriptions
8.6.1.6
I2C_Control_1 Register (Address = 5h) [reset = 1Eh]
Table 17.
I2C_Control_1 Register Field Descriptions
8.6.1.7
I2C_Control_2 Register (Address = 6h) [reset = 0h]
Table 18.
I2C_Control_2 Register Field Descriptions
8.6.1.8
REMOTE_ID Register (Address = 7h) [reset = 0h]
Table 19.
REMOTE_ID Register Field Descriptions
8.6.1.9
SlaveID_0 Register (Address = 8h) [reset = 0h]
Table 20.
SlaveID_0 Register Field Descriptions
8.6.1.10
SlaveID_1 Register (Address = 9h) [reset = 0h]
Table 21.
SlaveID_1 Register Field Descriptions
8.6.1.11
SlaveID_2 Register (Address = Ah) [reset = 0h]
Table 22.
SlaveID_2 Register Field Descriptions
8.6.1.12
SlaveID_3 Register (Address = Bh) [reset = 0h]
Table 23.
SlaveID_3 Register Field Descriptions
8.6.1.13
SlaveID_4 Register (Address = Ch) [reset = 0h]
Table 24.
SlaveID_4 Register Field Descriptions
8.6.1.14
SlaveID_5 Register (Address = Dh) [reset = 0h]
Table 25.
SlaveID_5 Register Field Descriptions
8.6.1.15
SlaveID_6 Register (Address = Eh) [reset = 0h]
Table 26.
SlaveID_6 Register Field Descriptions
8.6.1.16
SlaveID_7 Register (Address = Fh) [reset = 0h]
Table 27.
SlaveID_7 Register Field Descriptions
8.6.1.17
SlaveAlias_0 Register (Address = 10h) [reset = 0h]
Table 28.
SlaveAlias_0 Register Field Descriptions
8.6.1.18
SlaveAlias_1 Register (Address = 11h) [reset = 0h]
Table 29.
SlaveAlias_1 Register Field Descriptions
8.6.1.19
SlaveAlias_2 Register (Address = 12h) [reset = 0h]
Table 30.
SlaveAlias_2 Register Field Descriptions
8.6.1.20
SlaveAlias_3 Register (Address = 13h) [reset = 0h]
Table 31.
SlaveAlias_3 Register Field Descriptions
8.6.1.21
SlaveAlias_4 Register (Address = 14h) [reset = 0h]
Table 32.
SlaveAlias_4 Register Field Descriptions
8.6.1.22
SlaveAlias_5 Register (Address = 15h) [reset = 0h]
Table 33.
SlaveAlias_5 Register Field Descriptions
8.6.1.23
SlaveAlias_6 Register (Address = 16h) [reset = 0h]
Table 34.
SlaveAlias_6 Register Field Descriptions
8.6.1.24
SlaveAlias_7 Register (Address = 17h) [reset = 0h]
Table 35.
SlaveAlias_7 Register Field Descriptions
8.6.1.25
MAILBOX_18 Register (Address = 18h) [reset = 0h]
Table 36.
MAILBOX_18 Register Field Descriptions
8.6.1.26
MAILBOX_19 Register (Address = 19h) [reset = 1h]
Table 37.
MAILBOX_19 Register Field Descriptions
8.6.1.27
GPIO_9_Global_GPIO_Config Register (Address = 1Ah) [reset = 0h]
Table 38.
GPIO_9_Global_GPIO_Config Register Field Descriptions
8.6.1.28
Frequency_Counter Register (Address = 1Bh) [reset = 0h]
Table 39.
Frequency_Counter Register Field Descriptions
8.6.1.29
General_Status Register (Address = 1Ch) [reset = 0h]
Table 40.
General_Status Register Field Descriptions
8.6.1.30
GPIO0_Config Register (Address = 1Dh) [reset = 0h]
Table 41.
GPIO0_Config Register Field Descriptions
8.6.1.31
GPIO1_2_Config Register (Address = 1Eh) [reset = 0h]
Table 42.
GPIO1_2_Config Register Field Descriptions
8.6.1.32
GPIO_3_Config Register (Address = 1Fh) [reset = 0h]
Table 43.
GPIO_3_Config Register Field Descriptions
8.6.1.33
GPIO_5_6_Config Register (Address = 20h) [reset = 0h]
Table 44.
GPIO_5_6_Config Register Field Descriptions
8.6.1.34
GPIO_7_8_Config Register (Address = 21h) [reset = 0h]
Table 45.
GPIO_7_8_Config Register Field Descriptions
8.6.1.35
Datapath_Control Register (Address = 22h) [reset = 0h]
Table 46.
Datapath_Control Register Field Descriptions
8.6.1.36
RX_Mode_Status Register (Address = 23h) [reset = Strap]
Table 47.
RX_Mode_Status Register Field Descriptions
8.6.1.37
BIST_Control Register (Address = 24h) [reset = 8h]
Table 48.
BIST_Control Register Field Descriptions
8.6.1.38
BIST_ERROR_COUNT Register (Address = 25h) [reset = 0h]
Table 49.
BIST_ERROR_COUNT Register Field Descriptions
8.6.1.39
SCL_High_Time Register (Address = 26h) [reset = 83h]
Table 50.
SCL_High_Time Register Field Descriptions
8.6.1.40
SCL_Low_Time Register (Address = 27h) [reset = 84h]
Table 51.
SCL_Low_Time Register Field Descriptions
8.6.1.41
Datapath_Control_2 Register (Address = 28h) [reset = Loaded from SER]
Table 52.
Datapath_Control_2 Register Field Descriptions
8.6.1.42
I2S_Control Register (Address = 2Bh) [reset = 0h]
Table 53.
I2S_Control Register Field Descriptions
8.6.1.43
PCLK_Test_Mode Register (Address = 2Eh) [reset = 0h]
Table 54.
PCLK_Test_Mode Register Field Descriptions
8.6.1.44
DUAL_RX_CTL Register (Address = 34h) [reset = 1h]
Table 55.
DUAL_RX_CTL Register Field Descriptions
8.6.1.45
AEQ_CTL1 Register (Address = 35h) [reset = 0h]
Table 56.
AEQ_CTL1 Register Field Descriptions
8.6.1.46
MODE_SEL Register (Address = 37h) [reset = 0h]
Table 57.
MODE_SEL Register Field Descriptions
8.6.1.47
I2S_DIVSEL Register (Address = 3Ah) [reset = 0h]
Table 58.
I2S_DIVSEL Register Field Descriptions
8.6.1.48
Adaptive_EQ_Status Register (Address = 3Bh) [reset = 0h]
Table 59.
Adaptive_EQ_Status Register Field Descriptions
8.6.1.49
LINK_ERROR_COUNT Register (Address = 41h) [reset = 3h]
Table 60.
LINK_ERROR_COUNT Register Field Descriptions
8.6.1.50
HSCC_CONTROL Register (Address = 43h) [reset = 0h]
Table 61.
HSCC_CONTROL Register Field Descriptions
8.6.1.51
ADAPTIVE_EQ_BYPASS Register (Address = 44h) [reset = 60h]
Table 62.
ADAPTIVE_EQ_BYPASS Register Field Descriptions
8.6.1.52
ADAPTIVE_EQ_MIN_MAX Register (Address = 45h) [reset = 88h]
Table 63.
ADAPTIVE_EQ_MIN_MAX Register Field Descriptions
8.6.1.53
CML_OUTPUT_CTL1 Register (Address = 52h) [reset = 0h]
Table 64.
CML_OUTPUT_CTL1 Register Field Descriptions
8.6.1.54
CML_OUTPUT_ENABLE Register (Address = 56h) [reset = 0h]
Table 65.
CML_OUTPUT_ENABLE Register Field Descriptions
8.6.1.55
CML_OUTPUT_CTL2 Register (Address = 57h) [reset = 0h]
Table 66.
CML_OUTPUT_CTL2 Field Descriptions
8.6.1.56
CML_OUTPUT_CTL3 Register (Address = 63h) [reset = 0h]
Table 67.
CML_OUTPUT_CTL3 Field Descriptions
8.6.1.57
PGCTL Register (Address = 64h) [reset = 10h]
Table 68.
PGCTL Register Field Descriptions
8.6.1.58
PGCFG Register (Address = 65h) [reset = 0h]
Table 69.
PGCFG Register Field Descriptions
8.6.1.59
PGIA Register (Address = 66h) [reset = 0h]
Table 70.
PGIA Register Field Descriptions
8.6.1.60
PGID Register (Address = 67h) [reset = 0h]
Table 71.
PGID Register Field Descriptions
8.6.1.61
PGDBG Register (Address = 68h) [reset = 0h]
Table 72.
PGDBG Register Field Descriptions
8.6.1.62
PGTSTDAT Register (Address = 69h) [reset = 0h]
Table 73.
PGTSTDAT Register Field Descriptions
8.6.1.63
CSICFG0 Register (Address = 6Ah) [reset = 0h]
Table 74.
CSICFG0 Register Field Descriptions
8.6.1.64
CSICFG1 Register (Address = 6Bh) [reset = 0h]
Table 75.
CSICFG1 Register Field Descriptions
8.6.1.65
CSIIA Register (Address = 6Ch) [reset = 0h]
Table 76.
CSIIA Register Field Descriptions
8.6.1.66
CSIID Register (Address = 6Dh) [reset = 0h]
Table 77.
CSIID Register Field Descriptions
8.6.1.67
GPIO_Pin_Status_1 Register (Address = 6Eh) [reset = 0h]
Table 78.
GPIO_Pin_Status_1 Register Field Descriptions
8.6.1.68
GPIO_Pin_Status_2 Register (Address = 6Fh) [reset = 0h]
Table 79.
GPIO_Pin_Status_2 Register Field Descriptions
8.6.1.69
ID0 Register (Address = F0h) [reset = 5Fh]
Table 80.
ID0 Register Field Descriptions
8.6.1.70
ID1 Register (Address = F1h) [reset = 55h]
Table 81.
ID1 Register Field Descriptions
8.6.1.71
ID2 Register (Address = F2h) [reset = 48h]
Table 82.
ID2 Register Field Descriptions
8.6.1.72
ID3 Register (Address = F3h) [reset = 39h]
Table 83.
ID3 Register Field Descriptions
8.6.1.73
ID4 Register (Address = F4h) [reset = 34h]
Table 84.
ID4 Register Field Descriptions
8.6.1.74
ID5 Register (Address = F5h) [reset = 30h]
Table 85.
ID5 Register Field Descriptions
8.6.2
CSI-2 Indirect Registers
8.6.2.1
CSI_TCK_PREP Register (Address = 0h) [reset = 0h]
Table 87.
CSI_TCK_PREP Register Field Descriptions
8.6.2.2
CSI_TCK_ZERO Register (Address = 1h) [reset = 0h]
Table 88.
CSI_TCK_ZERO Register Field Descriptions
8.6.2.3
CSI_TCK_TRAIL Register (Address = 2h) [reset = 0h]
Table 89.
CSI_TCK_TRAIL Register Field Descriptions
8.6.2.4
CSI_TCK_POST Register (Address = 3h) [reset = 0h]
Table 90.
CSI_TCK_POST Register Field Descriptions
8.6.2.5
CSI_THS_PREP Register (Address = 4h) [reset = 0h]
Table 91.
CSI_THS_PREP Register Field Descriptions
8.6.2.6
CSI_THS_ZERO Register (Address = 5h) [reset = 0h]
Table 92.
CSI_THS_ZERO Register Field Descriptions
8.6.2.7
CSI_THS_TRAIL Register (Address = 6h) [reset = 0h]
Table 93.
CSI_THS_TRAIL Register Field Descriptions
8.6.2.8
CSI_THS_EXIT Register (Address = 7h) [reset = 0h]
Table 94.
CSI_THS_EXIT Register Field Descriptions
8.6.2.9
CSI_TLPX Register (Address = 8h) [reset = 0h]
Table 95.
CSI_TLPX Register Field Descriptions
8.6.2.10
RAW_ALIGN Register (Address = 9h) [reset = 0h]
Table 96.
RAW_ALIGN Register Field Descriptions
8.6.2.11
CSI_EN_PORT0 Register (Address = 13h) [reset = 3Fh]
Table 97.
CSI_EN_PORT0 Register Field Descriptions
8.6.2.12
CSI_EN_PORT1 Register (Address = 14h) [reset = 0h]
Table 98.
CSI_EN_PORT1 Register Field Descriptions
8.6.2.13
CSIPASS Register (Address = 16h) [reset = 2h]
Table 99.
CSIPASS Register Field Descriptions
8.6.2.14
CSI_VC_ID Register (Address = 2Eh) [reset = 0h]
Table 100.
CSI_VC_ID Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
FPD-Link III Interconnect Guidelines
9.2.3
Application Curves
10
Power Supply Recommendations
10.1
Power-Up Requirements and PDB Pin
10.2
Power Sequence
11
Layout
11.1
Layout Guidelines
11.2
Ground
11.3
Routing FPD-Link III Signal Traces
11.4
CSI-2 Guidelines
11.5
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントのサポート
12.1.1
関連資料
12.2
ドキュメントの更新通知を受け取る方法
12.3
コミュニティ・リソース
12.4
商標
12.5
静電気放電に関する注意事項
12.6
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
NKD|64
MPQS032B
サーマルパッド・メカニカル・データ
NKD|64
QFND765
発注情報
jajsh34_oa
jajsh34_pm
7
Specifications