SNLS454A
November 2014 – March 2019
DS90UB947-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Applications Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
6.7
DC and AC Serial Control Bus Characteristics
6.8
Recommended Timing for the Serial Control Bus
6.9
Timing Diagrams
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
High-Speed Forward Channel Data Transfer
7.3.2
Back Channel Data Transfer
7.3.3
FPD-Link III Port Register Access
7.3.4
OpenLDI Input Frame and Color Bit Mapping Select
7.3.5
Video Control Signals
7.3.6
Power Down (PDB)
7.3.7
Serial Link Fault Detect
7.3.8
Interrupt Pin (INTB)
7.3.9
Remote Interrupt Pin (REM_INTB)
7.3.10
General-Purpose I/O
7.3.10.1
GPIO[3:0] Configuration
7.3.10.2
Back Channel Configuration
7.3.10.3
GPIO_REG[8:5] Configuration
7.3.11
SPI Communication
7.3.11.1
SPI Mode Configuration
7.3.11.2
Forward Channel SPI Operation
7.3.11.3
Reverse Channel SPI Operation
7.3.12
Backward Compatibility
7.3.13
Audio Modes
7.3.13.1
I2S Audio Interface
7.3.13.1.1
I2S Transport Modes
7.3.13.1.2
I2S Repeater
7.3.13.2
TDM Audio Interface
7.3.14
Repeater
7.3.14.1
Repeater Configuration
7.3.14.2
Repeater Connections
7.3.14.2.1
Repeater Fan-Out Electrical Requirements
7.3.15
Built-In Self Test (BIST)
7.3.15.1
BIST Configuration and Status
7.3.15.2
Forward Channel and Back Channel Error Checking
7.3.16
Internal Pattern Generation
7.3.16.1
Pattern Options
7.3.16.2
Color Modes
7.3.16.3
Video Timing Modes
7.3.16.4
External Timing
7.3.16.5
Pattern Inversion
7.3.16.6
Auto Scrolling
7.3.16.7
Additional Features
7.4
Device Functional Modes
7.4.1
Mode Select Configuration Settings (MODE_SEL[1:0])
7.4.2
FPD-Link III Modes of Operation
7.4.2.1
Single Link Operation
7.4.2.2
Dual Link Operation
7.4.2.3
Replicate Mode
7.4.2.4
Auto-Detection of FPD-Link III Modes
7.5
Programming
7.5.1
Serial Control Bus
7.5.2
Multi-Master Arbitration Support
7.5.3
I2C Restrictions on Multi-Master Operation
7.5.4
Multi-Master Access to Device Registers for Newer FPD-Link III Devices
7.5.5
Multi-Master Access to Device Registers for Older FPD-Link III Devices
7.5.6
Restrictions on Control Channel Direction for Multi-Master Operation
7.6
Register Maps
8
Application and Implementation
8.1
Applications Information
8.2
Typical Applications
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
High-Speed Interconnect Guidelines
8.2.3
Application Curves
8.2.3.1
Application Performance Plots
9
Power Supply Recommendations
9.1
Power-Up Requirements and PDB Pin
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Trademarks
11.3
Electrostatic Discharge Caution
11.4
Glossary
12
Mechanical, Packaging and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGC|64
MPQF125F
サーマルパッド・メカニカル・データ
RGC|64
QFND476B
発注情報
snls454a_oa
snls454a_pm
7.3.10
General-Purpose I/O