JAJSGI9D October   2014  – February 2022 DS90UB948-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Oscillator Output
      5. 7.3.5  Clock and Output Status
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Interrupt Pin — Functional Description and Usage (INTB_IN)
      9. 7.3.9  General-Purpose I/O (GPIO)
        1. 7.3.9.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.9.2 Back Channel Configuration
        3. 7.3.9.3 GPIO Register Configuration
      10. 7.3.10 SPI Communication
        1. 7.3.10.1 SPI Mode Configuration
        2. 7.3.10.2 Forward Channel SPI Operation
        3. 7.3.10.3 Reverse Channel SPI Operation
      11. 7.3.11 Backward Compatibility
      12. 7.3.12 Adaptive Equalizer
        1. 7.3.12.1 Transmission Distance
        2. 7.3.12.2 Adaptive Equalizer Algorithm
        3. 7.3.12.3 AEQ Settings
          1. 7.3.12.3.1 AEQ Start-Up and Initialization
          2. 7.3.12.3.2 AEQ Range
          3. 7.3.12.3.3 AEQ Timing
      13. 7.3.13 I2S Audio Interface
        1. 7.3.13.1 I2S Transport Modes
        2. 7.3.13.2 I2S Repeater
        3. 7.3.13.3 I2S Jitter Cleaning
        4. 7.3.13.4 MCLK
      14. 7.3.14 Repeater
        1. 7.3.14.1 Repeater Configuration
        2. 7.3.14.2 Repeater Connections
          1. 7.3.14.2.1 Repeater Fan-Out Electrical Requirements
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select MODE_SEL[1:0]
        1. 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
        5. 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
      2. 7.4.2 MODE_SEL[1:0]
        1. 7.4.2.1 Dual Swap
      3. 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
    5. 7.5 Image Enhancement Features
      1. 7.5.1 White Balance
      2. 7.5.2 LUT Contents
      3. 7.5.3 Enabling White Balance
        1. 7.5.3.1 LUT Programming Example
      4. 7.5.4 Adaptive Hi-FRC Dithering
    6. 7.6 Programming
      1. 7.6.1 Serial Control Bus
      2. 7.6.2 Multi-Controller Arbitration Support
      3. 7.6.3 I2C Restrictions on Multi-Controller Operation
      4. 7.6.4 Multi-Controller Access to Device Registers for Newer FPD-Link III Devices
      5. 7.6.5 Multi-Controller Access to Device Registers for Older FPD-Link III Devices
      6. 7.6.6 Restrictions on Control Channel Direction for Multi-Controller Operation
    7. 7.7 Register Maps
      1. 7.7.1 DS90UB948-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
        2. 8.2.2.2 AV Mute Prevention
        3. 8.2.2.3 Prevention of I2C Errors During Abrupt System Faults
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.1 Serial Control Bus

The device may also be configured by the use of a I2C-compatible serial control bus. Multiple devices may share the serial control bus (up to eight device addresses supported). The device address is set through a resistor divider (RHIGH and RLOW — see Figure 7-28 below) connected to the IDx pin.

GUID-55099679-AF47-47A2-B7AA-F4911B8FBACA-low.gifFigure 7-28 Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a serial bus clock input. SDA is the serial bus data input / output signal. Both SCL and SDA signals require an external pullup resistor to 1.8-V or 3.3-V VI2C. For most applications, TI recommends that the user adds a 4.7-kΩ pullup resistor to the VDD33 or 2.2 kΩ resistor to the VDD18. However, the pullup resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled high or driven low. For more details information on how to calculate the pullup resistor, see I2C Bus Pullup Resistor Calculation (SLVA689).

The IDx pin configures the control interface to one of eight possible device addresses. A pullup resistor and a pulldown resistor may be used to set the appropriate voltage ratio between the IDx input pin (VLOW) and VDD33, each ratio corresponding to a specific device address. See Table 7-11 for more information.

Table 7-11 Serial Control Bus Addresses for IDx
NO.VIDX
VOLTAGE		VIDX
TARGET VOLTAGE		SUGGESTED STRAP RESISTORS
(1% tolerance)		PRIMARY ASSIGNED I2C ADDRESS
V (TYP)VDD = 3.3 VR1 (kΩ)R2 (kΩ)7-BIT8-BIT
000Open100x2C0x58
10.169 x V(VDD33)0.55973.2150x2E0x5C
20.230 x V(VDD33)0.75766.5200x300x60
30.295 x V(VDD33)0.9745924.90x320x64
40.376 x V(VDD33)1.24149.930.10x340x68
50.466 x V(VDD33)1.53846.440.20x360x6C
60.556 x V(VDD33)1.83540.249.90x380x70
70.801 x V(VDD33)2.64218.7750x3C0x78

The serial bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions low while SCL is high. A STOP occurs when SCL transitions high while SDA is also HIGH. See Figure 7-29.

GUID-83C3663C-C7AA-4775-A55B-9DAEAAF3A22C-low.gifFigure 7-29 START and STOP Conditions

To communicate with a remote device, the host controller sends the Target address and listens for a response from the Target. This response is referred to as an acknowledge bit (ACK). If a Target on the bus is addressed correctly, it acknowledges (ACKs) the Controller by driving the SDA bus low. If the address does not match the Target address of a device, the Target not-acknowledges (NACKs) the Controller by letting the SDA be pulled High. ACKs also occur on the bus when data is transmitted. When the Controller writes data, the Target sends an ACK after every data byte is successfully received. When the Controller reads data, the Controller sends an ACK after every data byte is received to let the Target know that the Controller is ready to receive another data byte. When the Controller wants to stop reading, the Controller sends a NACK after the last data byte to create a stop condition on the bus. All communication on the bus begins with either a start condition or a repeated Start condition. All communication on the bus ends with a stop condition. A READ is shown in Figure 7-30 and a WRITE is shown in Figure 7-31.

Figure 7-30 Serial Control Bus — READ
Figure 7-31 Serial Control Bus — WRITE

The I2C Controller located in the deserializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to the I2C Communication Over FPD-Link III with Bidirectional Control Channel (SNLA131).

Note: I2C access over the BCC requires each transaction be terminated with a STOP rather than a repeated START.
Note: Serial Control Bus does not spport short format read over the BCC