JAJSGI9D October   2014  – February 2022 DS90UB948-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Oscillator Output
      5. 7.3.5  Clock and Output Status
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Interrupt Pin — Functional Description and Usage (INTB_IN)
      9. 7.3.9  General-Purpose I/O (GPIO)
        1. 7.3.9.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.9.2 Back Channel Configuration
        3. 7.3.9.3 GPIO Register Configuration
      10. 7.3.10 SPI Communication
        1. 7.3.10.1 SPI Mode Configuration
        2. 7.3.10.2 Forward Channel SPI Operation
        3. 7.3.10.3 Reverse Channel SPI Operation
      11. 7.3.11 Backward Compatibility
      12. 7.3.12 Adaptive Equalizer
        1. 7.3.12.1 Transmission Distance
        2. 7.3.12.2 Adaptive Equalizer Algorithm
        3. 7.3.12.3 AEQ Settings
          1. 7.3.12.3.1 AEQ Start-Up and Initialization
          2. 7.3.12.3.2 AEQ Range
          3. 7.3.12.3.3 AEQ Timing
      13. 7.3.13 I2S Audio Interface
        1. 7.3.13.1 I2S Transport Modes
        2. 7.3.13.2 I2S Repeater
        3. 7.3.13.3 I2S Jitter Cleaning
        4. 7.3.13.4 MCLK
      14. 7.3.14 Repeater
        1. 7.3.14.1 Repeater Configuration
        2. 7.3.14.2 Repeater Connections
          1. 7.3.14.2.1 Repeater Fan-Out Electrical Requirements
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select MODE_SEL[1:0]
        1. 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
        5. 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
      2. 7.4.2 MODE_SEL[1:0]
        1. 7.4.2.1 Dual Swap
      3. 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
    5. 7.5 Image Enhancement Features
      1. 7.5.1 White Balance
      2. 7.5.2 LUT Contents
      3. 7.5.3 Enabling White Balance
        1. 7.5.3.1 LUT Programming Example
      4. 7.5.4 Adaptive Hi-FRC Dithering
    6. 7.6 Programming
      1. 7.6.1 Serial Control Bus
      2. 7.6.2 Multi-Controller Arbitration Support
      3. 7.6.3 I2C Restrictions on Multi-Controller Operation
      4. 7.6.4 Multi-Controller Access to Device Registers for Newer FPD-Link III Devices
      5. 7.6.5 Multi-Controller Access to Device Registers for Older FPD-Link III Devices
      6. 7.6.6 Restrictions on Control Channel Direction for Multi-Controller Operation
    7. 7.7 Register Maps
      1. 7.7.1 DS90UB948-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
        2. 8.2.2.2 AV Mute Prevention
        3. 8.2.2.3 Prevention of I2C Errors During Abrupt System Faults
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN/FREQ.MINTYPMAXUNIT
POWER CONSUMPTION
PTTotal power consumption, normal operationPCLK = 170 MHz.
2-lane FPD-Link III input, dual-link OLDI output		VDD8581146mW
PZTotal power consumption, power-down modePDB = 0 V4070mW
SUPPLY CURRENT
IDD12Supply current, normal operationPCLK = 170 MHz.
2-lane FPD-Link III input, dual-link OLDI output		VDD12 = 1.2 V169223mA
IDD33VDD33 = 3.6 V168222mA
IDDIOVDDIO = 1.89 V or 3.6 V1419mA
IDD12Supply current, normal operationPCLK = 192 MHz
2-lane FPD-Link III input, dual link OLDI Output		VDD12 = 1.2 V189mA
VDD33 = 3.6 V188mA
IDD33
IDDIOVDDIO = 1.89 V or 3.6 V16mA
IDD12ZSupply current, power-down modePDB = 0 VVDD12 = 1.2 V230mA
IDD33ZVDD33 = 3.6 V28mA
IDDIOZVDDIO = 1.89 V or 3.6 V0.11mA
3.3-V LVCMOS I/O (V(VDDIO) = 3.3 V ± 10%)
VIHHigh level input voltagePDB, BISTEN2V(VDDIO)V
VILLow level input voltage00.8V
VIHHigh level input voltageBISTC, GPIO[3:0], D_GPIO[3:0], I2S_DA, I2S_DB, I2S_DC, I2S_DD, I2S_CLK, I2S_WC, LOCK, PASS2V(VDDIO)V
VILLow level input voltage00.8V
IINInput currentVIN = 0 V or V(VDDIO)–1010µA
IIN-STRAPStrap pin input currentVIN = 0V or V(VDD33)IDX, MODE_SEL0, MODE_SEL1-11µA
VOHHigh level output voltageIOH = –4 mABISTC, GPIO[3:0], D_GPIO[3:0], I2S_DA, I2S_DB, I2S_DC, I2S_DD, I2S_CLK, I2S_WC, LOCK, PASS2.4V(VDDIO)V
VOLLow level output voltageIOL = 4 mA00.4V
IOSOutput short-circuit currentVOUT = 0 V–55mA
IOZTri-state output currentPDB = 0 V
VOUT = 0 V or V(VDDIO)		–2020µA
CINInput capacitance10pF
1.8-V LVCMOS I/O (V(VDDIO) = 1.8 V ± 5%)
VIHHigh level input voltagePDB, BISTEN1.5V(VDDIO)V
VILHigh level input voltage00.35 × V(VDDIO)V
VIHHigh level input voltageBISTC, GPIO[3:0], D_GPIO[3:0], I2S_DA, I2S_DB, I2S_DC, I2S_DD, I2S_CLK, I2S_WC, LOCK, PASS0.65 × V(VDDIO)V(VDDIO)V
VILLow level input voltage00.35 × V(VDDIO)V
IINInput currentVIN = 0V or V(VDDIO)–1010µA
VOHHigh level output voltageIOH = –4 mAV(VDDIO) – 0.45V(VDDIO)V
VOLLow level output voltageIOL = 4 mA00.45V
IOSOutput short-circuit currentVOUT = 0 V–35mA
IOZTri-state output currentPDB = 0 V
VOUT = 0 V or V(VDDIO)		–2020µA
CINInput capacitance10pF
SERIAL CONTROL BUS (V(VDDIO) = 1.8 V ± 5% OR 3.3V ±10%)
VIHInput high levelV(VDDIO) = 3.0 V to 3.6 VI2C_SDA, I2C_SCL2V(VDDIO)V
VILInput low level00.9V
VIHInput high levelV(VDDIO) = 1.71 V to 1.89 V1.58V(VDDIO)V
VILInput low levelGND0.9V
VHYSInput hysteresis50mV
VOLOutput low levelIOL = 4 mA00.4V
IINInput currentVIN = 0 V or V(VDDIO)–1010µA
FPD-LINK III INPUT
VTHDifferential threshold high voltageVCM = 2.1 VRIN0+, RIN0–
RIN1+, RIN1–		50mV
VTLDifferential threshold low voltage–50mV
VIDInput differential threshold100mV
VCMDifferential common-mode voltage2.1V
RTInternal termination resistor - differential80100120Ω
LVDS DRIVER
VODOutput voltage swing (differential)RL =100 Ω, VOD Setting 1. See Figure 6-9.
See Section 7.7 Register 0x4B for configuration details.		D0±, D1±, D2±, D3±, D4±, D5±, D6±, D7±, CLK1±, CLK2±220380540mVP-P
RL =100 Ω, VOD Setting 2. See Figure 6-9.
See Section 7.7 Register 0x4B for configuration details.		370550730mVP-P
RL = 100 Ω, VOD Setting 3. See Figure 6-9.
See Section 7.7 Register 0x4B for configuration details.		460650840mVP-P
RL = 100 Ω, VOD Setting 4. See Figure 6-9.
See Section 7.7 Register 0x4B for configuration details.		530750970mVP-P
ΔVODChange in VOD between complementary output statesRL = 100 Ω150mV
VOSOffset voltageRL = 100 Ω. See Figure 6-9.1.1251.21.375V
ΔVOSChange in VOS between complementary Output StatesRL = 100 Ω150mV
IOSOutput short-circuit current-20mA
IOZOutput tri-state LVDS driver currentPDB = 0 V–500500µA
LOOP-THROUGH MONITOR OUTPUT
VODDifferential output voltageRL = 100 ΩCMLOUTP, CMLOUTN360mV