JAJSHF5 May 2019 DS90UB949A-Q1
PRODUCTION DATA.
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in Figure 28.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VDDIO | 1.8 V |
STP configuration, AC-coupling capacitor for DOUT0± and DOUT1± with DS90Ux92x-Q1 deserializers.
Note the 92x does not support single-ended coax unless specifically specified. |
100 nF |
STP/STQ configuration, AC-coupling capacitor for DOUT0± and DOUT1± with DS90Ux94x-Q1 deserializers | 33 nF or 100 nF |
Coax configuration, AC-coupling capacitor for DOUT0± and DOUT1± with DS90Ux94x-Q1 deserializers | 100 nF on DOUT0/1+; 47nF on DOUT0/1–
or 33 nF on DOUT0/1+; 15nF on DOUT0/1– |
For applications that use a single-ended, 50-Ω coaxial cable, the unused data pins (DOUT0–, DOUT1–) should use a 15-nF capacitor and should be terminated with a 50-Ω resistor.
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC-coupling capacitor. This will help minimize degradation of signal quality due to package parasitics.