JAJSDW4 データシート

JAJSDW4C August 2017 – January 2023 DS90UB954-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGZ|48
- MPQF123F

サーマルパッド・メカニカル・データ

RGZ|48
- QFND014T

発注情報

8.1.2 Power Over Coax

The DS90UB54-Q1 is designed to support the Power-over-Coax (PoC) method of powering remote sensor systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed digital video data and bidirectional control and diagnostics data transmission. The method uses passive networks or filters that isolate the transmission line from the loading of the DC/DC regulator circuits and their connecting power traces on both sides of the link as shown in #SNLS47910566.

Figure 8-1 Power Over Coax (PoC) System Diagram

The PoC networks' impedance of ≥ 1 kΩ over a specific frequency band is recommended to isolate the transmission line from the loading of the regulator circuits. Higher PoC network impedance will contribute to favorable insertion loss and return loss characteristics in the high-speed channel. The lower limit of the frequency band is defined as ½ of the frequency of the bidirectional control channel, f_BCC. The upper limit of the frequency band is the frequency of the forward high-speed channel, f_FC. However, the main criteria that need to be met in the total high-speed channel, which consists of a serializer PCB, a deserializer PCB, and a cable, are the insertion loss and return loss limits defined in the Total Channel Requirements, while the system is under maximum current load and extreme temperature conditions⁽¹⁾⁽²⁾.

Contact TI for more information on the required Channel Specifications defined for each individual FPD-Link device.
The PoC network and any components along the high-speed trace on the PCB will contribute to the PCB loss budget. TI has recommendations for the loss budget allocation for each individual PCB and cable component in the overall high-speed channel, but the loss limits defined for the total channel in the Channel Specifications must be met.

#SNLS4791057 shows a PoC network recommended for a 4G FPD-Link III consisting of DS90UB953-Q1 and DS90UB954-Q1 pair with the bidirectional channel operating at 50 Mbps ( ½ f_BCC = 25 MHz) and the forward channel operating at 4.16 Gbps (f_FC ≈ 2.1 GHz).

Figure 8-2 Typical PoC Network for a 4G FPD-Link III

Table 8-1 lists essential components for this particular PoC network.

Table 8-1 Suggested Components for a 4G FPD-Link PoC Network

COUNT	REF DES	DESCRIPTION	PART NUMBER	MFR
1	L1	Inductor, 10 µH, 0.288 Ω maximum, 530 mA minimum (Isat, Itemp) 30-MHz SRF min, 3 mm × 3 mm, General-Purpose	LQH3NPN100MJR	Murata
		Inductor, 10 µH, 0.288 Ω maximum, 530 mA minimum (Isat, Itemp) 30-MHz SRF min, 3 mm × 3 mm, AEC-Q200	LQH3NPZ100MJR	Murata
		Inductor, 10 µH, 0.360 Ω maximum, 450 mA minimum (Isat, Itemp) 30-MHz SRF min, 3.2 mm x 2.5 mm, AEC-Q200	NLCV32T-100K-EFD	TDK
		Inductor, 10 µH, 0.400 Ω typical, 550 mA minimum (Isat, Itemp) 39-MHz SRF typ, 3 mm × 3 mm, AEC-Q200	TYS3010100M-10	Laird
		Inductor, 10 µH, 0.325 Ω maximum, 725 mA minimum (Isat, Itemp) 41-MHz SRF typ, 3 mm × 3 mm, AEC-Q200	TYS3015100M-10	Laird
3	FB1-FB3	Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC 500 mA at 85°C, 0603 SMD , General-Purpose	BLM18HE152SN1	Murata
3	FB1-FB3	Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC 500 mA at 85°C, 0603 SMD , AEC-Q200	BLM18HE152SZ1	Murata

#SNLS47910566B shows a PoC network recommended for a 2G FPD-Link III consisting of a DS90UB933-Q1 or DS90UB913A-Q1 serializer and DS90UB954-Q1 with the bidirectional channel operating at the data rate of 5 Mbps (½ f_BCC = 2.5 MHz) and the forward channel operating at the data rate as high as 1.87 Gbps (f_FC ≈ 1 GHz).

Figure 8-3 Typical PoC Network for a 2G FPD-Link III

Table 8-2 lists essential components for this particular PoC network.

Table 8-2 Suggested Components for a 2G FPD-Link III PoC Network

COUNT	REF DES	DESCRIPTION	PART NUMBER	MFR
1	L1	Inductor, 100 µH, 0.310 Ω maximum, 710 mA minimum (Isat, Itemp) 7.2-MHz SRF typical, 6.6 mm × 6.6 mm, AEC-Q200	MSS7341-104ML	Coilcraft
1	L2	Inductor, 4.7 µH, 0.350 Ω maximum, 700 mA minimum (Isat, Itemp) 160-MHz SRF typical, 3.8 mm x 3.8 mm, AEC-Q200	1008PS-472KL	Coilcraft
1	L2	Inductor, 4.7 µH, 0.130 Ω maximum, 830 mA minimum (Isat, Itemp), 70-MHz SRF typical, 3.2 mm × 2.5 mm, AEC-Q200	CBC3225T4R7MRV	Taiyo Yuden
1	FB1	Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC 500 mA at 85°C, 0603 SMD , General-Purpose	BLM18HE152SN1	Murata
1	FB1	Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC 500 mA at 85°C, 0603 SMD , AEC-Q200	BLM18HE152SZ1	Murata

Application report Sending Power over Coax in DS90UB913A Designs (SNLA224) discusses defining PoC networks in more detail.

In addition to the PoC network components selection, their placement and layout play a critical role as well.

Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as possible. Route the high-speed trace through one of its pads to avoid stubs.
Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner planes below the component pads to minimize impedance drop.
Consult with connector manufacturer for optimized connector footprint. If the connector is mounted on the same side as the IC, minimize the impactof the through-hole connector stubs by routing the high-speed signal traces on the opposite side of the connector mounting side.
Use coupled 100-Ω differential signal traces from the device pins to the AC-coupling caps. Use 50-Ω single-ended traces from the AC-coupling capacitors to the connector.
Terminate the inverting signal traces close to the connectors with standard 49.9-Ω resistors.

The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer boards are detailed in Table 8-3. The effects of the PoC networks must be accounted for when testing the traces for compliance to the suggested limits.

Table 8-3 Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks

PARAMETER		MIN	TYP	MAX	UNIT
L_trace	Single-ended PCB trace length from the device pin to the connector pin			5	cm
Z_trace	Single-ended PCB trace characteristic impedance	45	50	55	Ω
Z_con	Connector (mounted) characteristic impedance	40	50	60	Ω
t_{ΔZ_con}	Allowable electrical length of the connector impedance discontinuity as measured with a TDR (100 ps edge)			20	ps

The V_POC noise must be kept to 10 mVp-p or lower on the source / deserializer side of the system. The V_POC fluctuations on the serializer side, caused by the transient current draw of the sensor and the DC resistance of cables and PoC components,must be kept at minimum as well. Increasing the V_POC voltage and adding extra decoupling capacitance (> 10 µF) help reduce the amplitude and slew rate of the V_POC fluctuations.