5 Pin Configuration and Functions

Figure 5-1 RGZ Package48-Pin VQFN Top View

Table 5-1 Pin Functions

PIN		I/O TYPE	DESCRIPTION
NAME	NO.	I/O TYPE	DESCRIPTION
RECEIVE DATA CSI-2 OUTPUT
CSI_D3P	24	O	RECEIVE DATA OUTPUT: This signal carries data from the FPD-LINK III Deserializer to the processor over CSI-2 interface. Receive data is CSI-2 configured with DPHY outputs as one differential clock lane (CSI_CLK0P/N) and up to four differential data lanes (CSI_D0P/N: CSI_D3P/N) or two clock lanes (CSI_CLK0P/N, CSI_CLK1P/N) and two differential data lanes for each clock. When in replicate mode data lanes CSI_D2P/N and CSI_D3P/N are associated with clock lane CSI_CLK1P/N to provide the replicated output. For unused outputs leave as No Connect.
CSI_D3N	23
CSI_D2P	22
CSI_D2N	21
CSI_CLK1P	19
CSI_CLK1N	18
CSI_D1P	16
CSI_D1N	15
CSI_D0P	14
CSI_D0N	13
CSI_CLK0P	12
CSI_CLK0N	11
CLOCK INTERFACE
XOUT	4	O	Crystal oscillator output: Output Pin for providing crystal oscillator reference. Leave this pin NC when reference clock input is driving XIN/REFCLK.
XIN/REFCLK	5	S, I	Reference clock input or crystal oscillator input. Pin is shared with XIN and REFCLK. Typically REFCLK connected to 23- to 26-MHz reference oscillator output (100 ppm) or XIN configured with external 23- to 26-MHz crystal to XOUT. See GUID-2AEE12D3-ECAF-41A8-B7AD-95287127AA19.html#GUID-2AEE12D3-ECAF-41A8-B7AD-95287127AA19.
SYNCHRONIZATION AND GPIO
GPIO0	28	I/O, PD	General-Purpose Input/Output: Pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPIOs on the serializer or they may be configured to be outputs to follow local register settings. At power up, the GPIO are disabled and by default include a 35-k (typical) pulldown resistor. See GUID-91A6F2CA-9BFB-4FF2-B595-1AF3C9C5008B.html#GUID-91A6F2CA-9BFB-4FF2-B595-1AF3C9C5008B for programmability. Unused GPIO can be left open or no connect.
GPIO1	27
GPIO2	26
GPIO4	10
GPIO5	9
GPIO6	8
GPIO3/INTB	25	I/O, OD	General-Purpose Input/Output: Pin GPIO3 can be configured to be input signals for GPOs on the Serializer. Pin 25 is shared with INTB. Pullup with 4.7 kΩ to V_(VDDIO). The programmable input and output pin is an active-low open drain and controlled by the status registers. See GUID-91A6F2CA-9BFB-4FF2-B595-1AF3C9C5008B.html#GUID-91A6F2CA-9BFB-4FF2-B595-1AF3C9C5008B for programmability. Unused GPIO can be left open or no connect.
FPD-LINK III INTERFACE
RIN0+	41	I/O	Receive Input Channel 0: Differential FPD-Link receiver and bidirectional control back channel output. The IO must be AC coupled. See Design Requirements for the correct AC-coupling capacitor values. If port is unused, leave NC and set RX_PORT_CTL register bit 0 = 0 to disable (see GUID-5AF6E34F-6C1D-4A10-BAFB-50D60A86E3DD.html#GUID-5AF6E34F-6C1D-4A10-BAFB-50D60A86E3DD).
RIN0–	42	I/O
RIN1+	32	I/O	Receive Input Channel 1: Differential FPD-Link receiver and bidirectional control back channel output. The IO must be AC coupled. See Design Requirements for the correct AC-coupling capacitor values. If port is unused, leave NC and set RX_PORT_CTL register bit 1 = 0 to disable (see GUID-5AF6E34F-6C1D-4A10-BAFB-50D60A86E3DD.html#GUID-5AF6E34F-6C1D-4A10-BAFB-50D60A86E3DD).
RIN1–	33	I/O
I2C PINS
I2C_SCL	2	I/O, OD	I2C Serial Clock: Clock line for the bidirectional control bus communication. External 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See GUID-87576617-2B7A-4A14-BB18-B376680F1965.html#GUID-87576617-2B7A-4A14-BB18-B376680F1965 for more information.
I2C_SDA	1	I/O, OD	I2C Serial Data: Data line for bidirectional control bus communication. External 2-kΩ to 4.7-kΩ pullup resistor to 1.8-V or 3.3-V supply rail recommended per I2C interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See GUID-87576617-2B7A-4A14-BB18-B376680F1965.html#GUID-87576617-2B7A-4A14-BB18-B376680F1965 for more information.
CONFIGURATION AND CONTROL PINS
VDD_SEL	46	S, PD	VDD Select: Configuration pin to select internal LDO regulator supply. When VDD_SEL = LOW, internal 1.1-V supply mode is selected. Feed 1.8 V to VDD18 inputs = 1.8 V ±5%. An internal 1.1-V regulator will supply the VDD11. VDD11 inputs should be terminated with bypass capacitors. When VDD_SEL = HIGH, external 1.1-V supply mode is selected. After 1.8-V supply is applied to VDD18 inputs, then apply 1.1 V to VDD11 inputs = 1.1 V ±5%. Voltage at VDD11 supply pins must always be less than main voltage applied to VDD18 when using external 1.1-V supply.
IDX	35	S, PD	Input. I2C Serial Control Bus Primary Device ID Address Select. Once enabled the voltage at this pin will be sampled to configure the default I2C device address. Typically connected with external pullup resistor to VDD18 and pulldown resistor to GND to create a voltage divider. See Table 7-15.
MODE	37	S, PD	Mode select configuration input to set operating mode based on input voltage level. Typically connected to voltage divider through external pullup to VDD18 and pulldown to GND. See Table 7-2.
PDB	30	I, PD	Power-down inverted Input Pin. Typically connected to processor GPIO with pull down. When PDB input is brought HIGH, the device is enabled and internal register and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power with CSI-2 Tx outputs in tri-state. The default function of this pin is PDB = LOW; POWER DOWN with internal 50 kΩ pull down enabled. PDB should remain low until after power supplies are applied and reach minimum required levels. PDB INPUT IS 3.3-V TOLERANT. See section GUID-C21665F1-6728-482C-BFD5-5F6E27F2032D.html. PDB = 1.8 V, device is enabled (normal operation) PDB = 0, device is powered down.
DIAGNOSTIC PINS
CMLOUTP	38	O	Monitor Loop-Through Driver differential output. Typically routed to test points and not connected. For monitoring, CMLOUT should be terminated with 100-Ω differential load. See GUID-6B70EB6D-B946-4F10-B6F9-0C02B7A87BC6.html#GUID-6B70EB6D-B946-4F10-B6F9-0C02B7A87BC6.
CMLOUTN	39	O
BISTEN	6	S, PD	BIST Enable: BISTEN = H, BIST Mode is enabled BISTEN = L, BIST Mode is disabled. If unused connect BISTEN directly to GND. See BIST section GUID-56D2BB6B-5AA5-412B-997D-14210A3E859B.html#GUID-56D2BB6B-5AA5-412B-997D-14210A3E859B for more information.
PASS	47	O	PASS Output: PASS = H indicates pass conditions are met and PASS = L signals or more pass condition is not met. Typically route to processor input pin or test point for monitoring. May also be configured to indicate logical AND of pass status when both Rx ports are enabled. See GUID-3157D705-A8D1-4592-8B0F-03FD685143C0.html#GUID-3157D705-A8D1-4592-8B0F-03FD685143C0 for more information. For BIST operation PASS = H, ERROR FREE Transmission in forward channel operation. PASS = L, one or more errors were detected in the received payload. See BIST section for more information. Leave No Connect if unused.
LOCK	48	O	LOCK Status: Output Pin for monitoring lock status of FPD-Link III channel, may be used as Link Status. LOCK = H, the FPD-Link III receiver is Locked and Rx Ports are active. LOCK = L, receiver is unlocked. May also be configured to indicate logical AND of lock status when both Rx ports are enabled. See GUID-3157D705-A8D1-4592-8B0F-03FD685143C0.html#GUID-3157D705-A8D1-4592-8B0F-03FD685143C0 for more information. Leave No Connect if unused.
RES	44	PD	RES must be tied to GND for normal operation.
POWER AND GROUND
VDDIO	7,29	P	VDDIO voltage supply input: The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to either a 1.8-V or 3.3-V supply rail. When VDDIO is connected to 1.8-V supply, VDDIO must be within ±100 mV of VDD18 to ensure output timing requirements are met. Each VDDIO pin requires a minimum 1-µF and 0.01-µF capacitor to GND.
VDD18_CSI	17	P	1.8-V (±5%) Power Supply. Requires 1-µF and 0.01-µF capacitors to GND.
VDD18_P0 VDD18_P1	45 36	P	1.8-V(±5%) Power Supplies. Requires 0.01-µF capacitors to GND at each VDD pin along with 10-µF bulk decoupling
VDD18_FPD0 VDD18_FPD1	40 31	P	1.8-V(±5%) Analog Power Supplies. Requires 10-µF, and 0.1-µF capacitors to GND at each VDD pin.
VDD11_FPD0	43	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor to GND Requires a 10-μF capacitor to GND shared with VDD11_FPD1 See sections Power Supply Recommendations and Typical Application for more information
VDD11_FPD1	34	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires a 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor to GND Requires a 10-μF capacitor to GND shared with VDD11_FPD0
VDD11_CSI	20	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires a 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor and a 10-μF capacitor to GND
VDD11_D	3	D, P	When VDD_SEL = LOW: Do not connect to 1.1-V power rail Requires a 0.1 to 0.01-µF capacitor and a 4.7-µF capacitor to GND When VDD_SEL = HIGH: Connect to external 1.1-V power rail Requires a 0.01-μF capacitor and a 1-μF capacitor to GND
GND	DAP	G	DAP is the large metal contact at the bottom side, located at the center of the QFN package. Connect to the ground plane (GND).

The definitions below define the functionality of the I/O cells for each pin. TYPE:

I = Input
O = Output
I/O = Input/Output
S = Configuration pin (All strap pins have internal pulldowns. If the default strap value is needed to be changed then use an external resistor.)
PD = Internal pulldown
OD = Open Drain
P, G = Power supply, ground
D = Decoupling pin for internal voltage rail