JAJSDW4 データシート

JAJSDW4C August 2017 – January 2023 DS90UB954-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGZ|48
- MPQF123F

サーマルパッド・メカニカル・データ

RGZ|48
- QFND014T

発注情報

7.5.8.2 FPD-Link III Receive Port Interrupts

For each FPD-Link III Receive port, multiple options are available for generating interrupts. Interrupt generation is controlled through the PORT_ICR_HI 0xD8 and PORT_ICR_LO 0xD9 registers. In addition, the PORT_ISR_HI 0xDA and PORT_ISR_LO 0xDB registers provide read-only status for the interrupts. Clearing of interrupt conditions is handled by reading the RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS registers. The status bits in the PORT_ISR_HI/LO registers are copies of the associated bits in the main status registers.

To enable interrupts from one of the Receive port interrupt sources:

Enable the interrupt source by setting the appropriate interrupt enable bit in the PORT_ICR_HI or PORT_ICR_LO register
Set the RX Port X Interrupt control bit (IE_RXx) in the INTERRUPT_CTL register
Set the INT_EN bit in the INTERRUPT_CTL register to allow the interrupt to assert the INTB pin low

To clear interrupts from one of the Receive port interrupt sources:

(optional) Read the INTERRUPT_STS register to determine which RX Port caused the interrupt
(optional) Read the PORT_ISR_HI and PORT_ISR_LO registers to determine source of interrupt
Read the appropriate RX_PORT_STS1, RX_PORT_STS2, or CSI_RX_STS register to clear the interrupt.

The first two steps are optional. The interrupt could be determined and cleared by just reading the status registers.